# US 11,451,240 B2 · Double data rate (DDR) quad switched multibit digital to analog converter and continuous time sigma-delta modulator

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- Number: US 11,451,240 B2
- Document ID: US11451240B2
- Status: Granted
- Kind: B2
- Application number: 17/344,450
- Filed: 2021-06-10
- Published: 2022-01-27
- Granted: 2022-09-20
- Earliest claimed: 2020-07-21
- Assignees: STMicroelectronics International N.V.
- Applicants: STMicroelectronics International N.V.
- Inventors: Vivek Tripathi
- Web page: https://patentgrep.com/patent/US11451240B2

## CPC

- H03M 7/165: {Conversion to or from thermometric code}
- H03M 1/0665: {using data dependent selection of the elements, e.g. data weighted averaging}
- H03M 3/37: {Compensation or reduction of delay or phase error}
- H03M 3/424: {the quantiser being a multiple bit one}
- H03M 3/44: {with provisions for rendering the modulator inherently stable}
- H03M 3/454: {with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage}
- H03M 3/464: {Details of the digital/analogue conversion in the feedback path}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A quad signal generator circuit generates four 2N-1 bit control signals in response to a 2N-1 bit thermometer coded signal. A digital-to-analog converter (DAC) circuit has 2N-1 unit DAC elements, with each unit DAC element including four switching circuits controlled by corresponding bits of the four 2N-1 bit control signals. Outputs of the 2N-1 unit DAC elements are summed to generate an analog output signal. The quad signal generator circuit controls a time delay applied to clock signals relative to the 2N-1 bit thermometer coded signal and a time delay applied to the 2N-1 bit thermometer coded signal relative to the delayed clock signals in logically generating the four 2N-1 bit control signals. The analog output signal may be a feedback signal in a sigma-delta analog-to-digital converter (ADC) circuit that includes a multi-bit quantization circuit operating to quantize a filtered loop signal to generate the 2N-1 bit thermometer coded signal.

## Claims

### Claim 1

A circuit, comprising:
a digital-to-analog converter (DAC) circuit having 2N-1 unit resistive DAC elements, wherein each unit resistive DAC element includes four switching circuits controlled by corresponding bits of four 2N-1 bit control signals, and wherein outputs of the 2N-1 unit resistive DAC elements are summed to generate an analog output signal; and
a quad signal generator circuit configured to generate the four 2N-1 bit control signals in response to a 2N-1 bit thermometer coded input signal, wherein the quad signal generator circuit comprises:
a clock phase circuit configured to generate first and second clock signals that are 180° out of phase with each other and apply a first delay to set clock edges of the first and second clock signals to trail logic switching of the 2N-1 bit thermometer coded input signal;
a first circuit configured to logically combine the 2N-1 bit thermometer coded input signal with the first clock signal to generate a first one of the four 2N-1 bit control signals;
a second circuit configured to logically combine a delay of the 2N-1 bit thermometer coded input signal with the second clock signal to generate a second one of the four 2N-1 bit control signals, wherein the second circuit applies a second delay to set the logic switching of the delayed 2N-1 bit thermometer coded input signal to trail the clock edges of the first and second clock signals;
a third circuit configured to logically combine a logical inversion of the 2N-1 bit thermometer coded input signal with the first clock signal to generate a third one of the four 2N-1 bit control signals; and
a fourth circuit configured to logically combine a delay of the logical inversion of the 2N-1 bit thermometer coded input signal with the second clock signal to generate a fourth one of the four 2N-1 bit control signals, wherein the fourth circuit applies a third delay to set the logic switching of the delayed logical inversion of the 2N-1 bit thermometer coded input signal to trail the clock edges of the first and second clock signals.

### Claim 2 (depends on 1)

The circuit of claim 1, wherein the clock phase circuit of the quad signal generator circuit further applies a frequency division to frequency divide a sampling clock having clock edges aligned with logic switching of the 2N-1 bit thermometer coded input signal to generate the first and second clock signals.

### Claim 3 (depends on 2)

The circuit of claim 2, wherein the frequency division is divide by two.

### Claim 4 (depends on 1)

The circuit of claim 1, wherein the clock phase circuit of the quad signal generator circuit derives the first and second clock signals from a sampling clock having clock edges aligned with logic switching of the 2N-1 bit thermometer coded input signal.

### Claim 5 (depends on 4)

The circuit of claim 4, wherein the first delay is less than one half of a clock period of the sampling clock.

### Claim 6 (depends on 5)

The circuit of claim 5, wherein the second and third delays are each less than one half of the clock period of the sampling clock.

### Claim 7 (depends on 6)

The circuit of claim 6, wherein a sum of the first delay and one of the second and third delays is less than one half of the clock period of the sampling clock.

### Claim 8 (depends on 4)

The circuit of claim 4, wherein the second and third delays are equal.

### Claim 9 (depends on 4)

The circuit of claim 4, wherein the second and third delays are each less than one half of a clock period of the sampling clock.

### Claim 10 (depends on 1)

The circuit of claim 1, wherein each switching circuit of said four switching circuits of each unit resistive DAC element comprises:
a first switching circuit configured to switch a first common node between a first and second reference voltages in response to said third one of the four 2N-1 bit control signals and a logical inversion of said first one of the four 2N-1 bit control signals;
a second switching circuit configured to switch a second common node between the first and second reference voltages in response to the fourth one of the four 2N-1 bit control signals and a logical inversion of the second one of the four 2N-1 bit control signals;
a third switching circuit configured to switch a third common node between the first and second reference voltages in response to the first one of the four 2N-1 bit control signals and a logical inversion of the third one of the four 2N-1 bit control signals; and
a fourth switching circuit configured to switch a fourth common node between the first and second reference voltages in response to the second one of the four 2N-1 bit control signals and a logical inversion of the fourth one of the four 2N-1 bit control signals.

### Claim 11 (depends on 10)

The circuit of claim 10, further comprising:
a first resistive circuit coupled between the first common node and a first summing output node for providing a first component of the analog output signal;
a second resistive circuit coupled between the second common node and the first summing output node for providing the first component of the analog output signal;
a third resistive circuit coupled between the third common node and a second summing output node for providing a second component of the analog output signal; and
a fourth resistive circuit coupled between the fourth common node and the second summing output node for providing the second component of the analog output signal.

### Claim 12 (depends on 11)

The circuit of claim 11, wherein the first and second components are differential currents of the analog output signal.

### Claim 13 (depends on 1)

The circuit of claim 1, wherein the 2N-1 bit thermometer coded input signal is generated with data weighted averaging (DWA).

### Claim 14 (depends on 13)

The circuit of claim 13, further including a DWA circuit configured to apply data weighted averaging to a received 2N-1 bit thermometer coded signal in order to generate the 2N-1 bit thermometer coded input signal.

### Claim 15 (depends on 14)

The circuit of claim 14, further including a multi-bit quantization circuit configured to generate the 2N-1 bit thermometer coded signal.

### Claim 16 (depends on 1)

The circuit of claim 1, further comprising a loop filter circuit configured to generate a difference signal from a difference between an analog input signal and said analog output signal and filter the difference signal to generate a change signal.

### Claim 17 (depends on 16)

The circuit of claim 16, further comprising a multi-bit quantization circuit configured to quantize the change signal and generate a 2N-1 bit thermometer coded signal from which the 2N-1 bit thermometer coded input signal is generated.

### Claim 18 (depends on 17)

The circuit of claim 17, further comprising a data weighted averaging (DWA) circuit configured to apply data weighted averaging to the 2N-1 bit thermometer coded signal in order to generate the 2N-1 bit thermometer coded input signal.

### Claim 19 (depends on 1)

The circuit of claim 1, wherein the first delay is less than one half of a clock period of the first and second clock signals.

### Claim 20 (depends on 19)

The circuit of claim 19, wherein the second and third delays are each less than one half of the clock period of the first and second clock signals.

### Claim 21 (depends on 20)

The circuit of claim 20, wherein a sum of the first delay and one of the second and third delays is less than one half of the clock period of the first and second clock signals.

### Claim 22 (depends on 1)

The circuit of claim 1, wherein the second and third delays are equal.

### Claim 23 (depends on 1)

The circuit of claim 1, wherein the second and third delays are each less than one half of a clock period of the first and second clock signals.