Power reduction and performance enhancement techniques for delta sigma modulator

A delta-sigma modulator comprising:

• a first clock phase signal and a second clock phase signal being non-overlapping with respect to each other;
• a summing node that sums an analog input signal and a feedback signal;
• a loop filter that filters the first summed analog signal according to a noise shaping function and outputs a filtered analog signal, the loop filter including:
• a double sampling integrator including a first capacitor path and a second capacitor path, wherein the first capacitor path samples the analog input signal and the second capacitor path integrates a sample during the first clock phase signal and wherein the second capacitor path integrates a sample and the second capacitor path samples the analog input signal during the second clock phase signal;
• a quantizer that quantizes the output of the of the double sampling integrator;
• a feedback path that connects an output of the quantizer to the summing node;
• and
• a holding filter on the feedback path,
• wherein the first capacitor path and the second capacitor path have a first sampling frequency,
• wherein the double sampling integrator has a second sampling frequency that is double the first sampling frequency,
• wherein an output of the quantizer is down-sampled by a predetermined factor to form a down-sampled signal which is output to the feedback path,
• wherein the down-sampled signal is up-sampled on the feedback path by the predetermined factor before being fed to the holding filter,
• wherein the up-sampled signal includes DAC codes, and
• wherein the holding filter keeps a value of the DAC code of the up-sampled signal at a constant level during each period of the first clock phase signal and the second clock phase signal to generate the feedback signal.

A delta-sigma ADC comprising:

• a first clock phase signal and a second clock phase signal being non-overlapping with respect to each other;
• a delta-sigma modulator including:
• a first summing node for summing an analog input signal and a feedback signal and outputting a first summed analog signal;
• a loop filter that filters the first summed analog signal according to a noise shaping function and outputs a filtered analog signal;
• a quantizer that quantizes the filtered analog signal and outputs a quantized output signal;
• a feedback path that connects an output of the quantizer with an input of the summing node;
• and
• a feedback DAC on the feedback path that receives the quantized output signal and converts the quantized output signal into the feedback signal which is supplied to the first summing node;
• and
• wherein the feedback DAC includes a switched capacitor circuit, the switched capacitor circuit including a plurality of unit elements, the switched capacitor circuit being configured to selectively connect each of the respective unit elements into different connection states depending on a DAC code of the quantized output signal, the different connection states including:
• a first connection state in which the respective unit element is connected to supply a first signal to an output of the feedback DAC, the first connection state corresponding to a first signal level;
• a second connection state in which the respective unit element is connected to supply a second signal to the output of the feedback DAC, the second connection state corresponding to a second signal level;
• and
• a third connection state in which the respective unit element is disconnected from the output of the feedback DAC, the third connection state corresponding to a third signal level, and
• wherein the loop filter includes a double sampling integrator having a first capacitor path and a second capacitor path, wherein the first capacitor path samples the analog input signal and the second capacitor path integrates a sample during the first clock phase signal and wherein the second capacitor path integrates a sample and the second capacitor path samples the analog input signal during the second clock phase signal,
• wherein the quantizer quantizes the output of the of the double sampling integrator,
• wherein the feedback path includes a holding filter,
• wherein the first capacitor path and the second capacitor path have a first sampling frequency,
• wherein the double sampling integrator has a second sampling frequency that is double the first sampling frequency,
• wherein an output of the quantizer is down-sampled by a predetermined factor to form a down-sampled signal which is output to the feedback path,
• wherein the down-sampled signal is up-sampled on the feedback path by the predetermined factor before being fed to the holding filter,
• wherein the up-sampled signal includes DAC codes, and
• wherein the holding filter keeps a value of the DAC code of the up-sampled signal at a constant level during each period of the first clock phase signal and the second clock phase signal to generate the feedback signal.