# US 11,451,237 B2 · Sample and hold circuit and method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,451,237 B2 - Document ID: US11451237B2 - Status: Granted - Kind: B2 - Application number: 17/353,858 - Filed: 2021-06-22 - Published: 2022-05-12 - Granted: 2022-09-20 - Earliest claimed: 2020-11-06 - Assignees: Realtek Semiconductor Corp. - Applicants: Realtek Semiconductor Corporation - Inventors: Shih-Hsiung Huang; Wei-Chou Wang; Chun-Hsiung Chang; Shun-Ta Wu - Web page: https://patentgrep.com/patent/US11451237B2 ## CPC - G11C 27/024: {using a capacitive memory element (G11C27/04 takes precedence)} - H03M 1/1245: {Details of sampling arrangements or methods} - G11C 27/02: Sample-and-hold arrangements (G11C27/04 takes precedence) - H03M 1/129: {Means for adapting the input signal to the range the converter can handle, e.g. limiting, pre-scaling (H03M1/18 takes precedence); Out-of-range indication} - H03M 1/468: {in which the input S/H circuit is merged with the feedback DAC array} - H03M 1/38: sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) - G11C: STATIC STORES (semiconductor memory devices H10B) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract Disclosed is a sample and hold circuit and method capable of amplifying an input signal. The method includes: in a sample phase, receiving a first (second) input signal with top electrodes of first (second) capacitors, and receiving the second (first) input signal with all bottom electrode(s) of at least a part of the first (second) capacitors; in a hold phase, stopping receiving the first (second) input signal with the top electrodes of the first (second) capacitors, and receiving a first (second) group of reference signals with the bottom electrodes of the first (second) capacitors, so that the first (second) capacitors provide a first (second) sample voltage on the top electrodes of the multiple first (second) capacitors through charge redistribution, wherein the first and second input signals are a pair of differential signals and they are opposite to each other. ## Claims ### Claim 1 A sample and hold circuit, comprising: a control circuit configured to generate a first input switch control signal and a first set of switch control signals, and to generate a second input switch control signal and a second set of switch control signals; a first input switch configured to be turn on according to the first input switch control signal in a sample phase and thereby transmit a first input signal, and to be turned off according to the first input switch control signal in a hold phase; a first set of switches configured to operate according to the first set of switch control signals; a first capacitor array including first capacitors coupled to the first input switch and the first set of switches, wherein top electrodes of the first capacitors receive the first input signal through the first input switch in the sample phase, all bottom electrode(s) of at least a part of the first capacitors receive(s) a second input signal through the first set of switches in the sample phase, the top electrodes of the first capacitors do not receive the first input signal in the hold phase, all bottom electrodes of the first capacitors receive a first group of reference signals through the first set of switches in the hold phase, and the first capacitors provide a first sample voltage on the top electrodes of the first capacitors by charge redistribution in the hold phase; a second input switch configured to be turn on according to the second input switch control signal in the sample phase and thereby transmit the second input signal, and to be turned off according to the second input switch control signal in the hold phase; a second set of switches configured to operate according to the second set of switch control signals; and a second capacitor array including second capacitors coupled to the second input switch and the second set of switches, wherein top electrodes of the second capacitors receive the second input signal through the second input switch in the sample phase, all bottom electrode(s) of at least a part of the second capacitors receive(s) the first input signal through the second set of switches in the sample phase, the top electrodes of the second capacitors do not receive the second input signal in the hold phase, all bottom electrodes of the second capacitors receive a second group of reference signals through the second set of switches in the hold phase, and the second capacitors provide a second sample voltage on the top electrodes of the second capacitors by charge redistribution in the hold phase. ### Claim 2 (depends on 1) The sample and hold circuit of claim 1, wherein the first capacitors are composed of the at least a part of the first capacitors and a remaining part of the first capacitors; all bottom electrode(s) of the remaining part of the first capacitors receive(s) a corresponding part of the first group of reference signals through the first set of switches in the sample phase; the second capacitors are composed of the at least a part of the second capacitors and a remaining part of the second capacitors; all bottom electrode(s) of the remaining part of the second capacitors receive(s) a corresponding part of the second group of reference signals through the second set of switches in the sample phase. ### Claim 3 (depends on 2) The sample and hold circuit of claim 2, wherein capacitance of the at least a part of the first capacitors is not less than capacitance of the remaining part of the first capacitors, and capacitance of the at least a part of the second capacitors is not less than capacitance of the remaining part of the second capacitors. ### Claim 4 (depends on 1) The sample and hold circuit of claim 1, wherein the first input signal and the second input signal are a pair of differential signals. ### Claim 5 (depends on 1) The sample and hold circuit of claim 1, wherein the first input signal is a signal voltage varying with time, and the second input signal is a constant voltage. ### Claim 6 A sample and hold method performed with a sample and hold circuit, the method comprising: receiving a first input signal with top electrodes of first capacitors in a sample phase, and receiving a second input signal with all bottom electrode(s) of at least a part of the first capacitors in the sample phase; stopping receiving the first input signal with the top electrodes of the first capacitors in a hold phase, receiving a first group of reference signals with all bottom electrodes of the first capacitors in the hold phase, and providing a first sample voltage on the top electrodes of the first capacitors by charge redistribution in the hold phase; receiving the second input signal with top electrodes of second capacitors in the sample phase, and receiving the first input signal with all bottom electrode(s) of at least a part of the second capacitors in the sample phase; and stopping receiving the second input signal with the top electrodes of the second capacitors in the hold phase, receiving a second group of reference signals with all bottom electrodes of the second capacitors in the hold phase, and providing a second sample voltage on the top electrodes of the second capacitors by charge redistribution in the hold phase. ### Claim 7 (depends on 6) The sample and hold method of claim 6, wherein the first capacitors are composed of the at least a part of the first capacitors and a remaining part of the first capacitors; the second capacitors are composed of the at least a part of the second capacitors and a remaining part of the second capacitors; and the sample and hold method further comprises: receiving a corresponding part of the first group of reference signals with all bottom electrode(s) of the remaining part of the first capacitors in the sample phase; and receiving a corresponding part of the second group of reference signals with all bottom electrode(s) of the remaining part of the second capacitors in the sample phase. ### Claim 8 (depends on 7) The sample and hold method of claim 7, wherein capacitance of the at least a part of the first capacitors is not less than capacitance of the remaining part of the first capacitors, and capacitance of the at least a part of the second capacitors is not less than capacitance of the remaining part of the second capacitors. ### Claim 9 (depends on 6) The sample and hold method of claim 6, wherein the first input signal and the second input signal are a pair of differential signals. ### Claim 10 (depends on 6) The sample and hold method of claim 6, wherein the first input signal is a signal voltage varying with time, and the second input signal is a constant voltage. ### Claim 11 A sample and hold method performed with a sample and hold circuit, the method comprising: receiving a first input signal with top electrodes of first capacitors in a sample phase, and receiving a first reference signal with all bottom electrode(s) of at least a part of the first capacitors in the sample phase; stopping receiving the first input signal with the top electrodes of the first capacitors in a hold phase, receiving a first group of reference signals with all bottom electrodes of the first capacitors in the hold phase, and providing a first sample voltage on the top electrodes of the first capacitors by charge redistribution in the hold phase; receiving a second input signal with top electrodes of second capacitors in the sample phase, and receiving a second reference signal with all bottom electrode(s) of at least a part of the second capacitors in the sample phase, wherein the second reference signal is different from the first reference signal; and stopping receiving the second input signal with the top electrodes of the second capacitors in the hold phase, receiving a second group of reference signals with all bottom electrodes of the second capacitors in the hold phase, and providing a second sample voltage on the top electrodes of the second capacitors by charge redistribution in the hold phase. ### Claim 12 (depends on 11) The sample and hold method of claim 11, wherein the first capacitors are composed of the at least a part of the first capacitors and a remaining part of the first capacitors; the second capacitors are composed of the at least a part of the second capacitors and a remaining part of the second capacitors; and the sample and hold method further comprises: receiving a corresponding part of the first group of reference signals with all bottom electrode(s) of the remaining part of the first capacitors in the sample phase; and receiving a corresponding part of the second group of reference signals with all bottom electrode(s) of the remaining part of the second capacitors in the sample phase. ### Claim 13 (depends on 12) The sample and hold method of claim 12, wherein capacitance of the at least a part of the first capacitors is not less than capacitance of the remaining part of the first capacitors, and capacitance of the at least a part of the second capacitors is not less than capacitance of the remaining part of the second capacitors. ### Claim 14 (depends on 11) The sample and hold method of claim 11, wherein the first input signal and the second input signal are a pair of differential signals. ### Claim 15 (depends on 11) The sample and hold method of claim 11, wherein the first input signal is a signal voltage varying with time, and the second input signal is a constant voltage.