# US 11,451,236 B2 · Metastabile state detection device and method, and ADC circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,451,236 B2 - Document ID: US11451236B2 - Status: Granted - Kind: B2 - Application number: 17/276,027 - Filed: 2020-05-09 - Published: 2022-04-07 - Granted: 2022-09-20 - Earliest claimed: 2019-12-26 - Assignees: Rigol Technologies Co., Ltd. - Applicants: Rigol Technologies Co., Ltd. - Inventors: Bo Yan; Junzhou Luo; Yue Wang; Tiejun Wang; Weisen Li - Web page: https://patentgrep.com/patent/US11451236B2 ## CPC - H03M 1/0863: {of switching transients, e.g. glitches} - H03M 1/1076: {Detection or location of converter hardware failure, e.g. power supply failure, open or short circuit} - H03L 7/081: provided with an additional controlled phase shifter {(H03L7/0998 takes precedence)} - H03M 1/1014: {at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error (gain setting for range control H03M1/18)} - H03M 1/12: Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) ## Abstract A metastable state detection device and method, and an ADC circuit are disclosed. The metastable state detection device includes: a delay unit which is configured to receive a synchronization signal and delay the synchronization signal based on preset step delay values; a first flip-flop unit including a first clock input terminal, a first data input terminal and a first data output terminal, wherein the first clock input terminal is configured to receive a clock signal; the first data input terminal is configured to receive the delayed synchronization signal; a second flip-flop unit including a second clock input terminal, a second data input terminal and a second data output terminal; a processing module connected to the second data output terminal, which is configured to receive a target clock signal and detect a metastable state of the first flip-flop unit according to the target clock signal. ## Claims ### Claim 1 A metastable state detection device comprising: a delay unit which is configured to receive a synchronization signal and delay the synchronization signal; a first flip-flop unit including a first clock input terminal, a first data input terminal and a first data output terminal, wherein the first clock input terminal is configured to receive a clock signal; the first data input terminal is connected to the delay unit and is configured to receive the delayed synchronization signal; a second flip-flop unit including a second clock input terminal, a second data input terminal and a second data output terminal, wherein the second clock input terminal is respectively connected to the delay unit and the first data input terminal and is configured to receive the delayed synchronization signal; the second data input terminal is connected to the first clock input terminal and is configured to receive a clock signal; the second data output terminal is configured to output a target clock signal that is synchronized with the delayed synchronization signal; a processing module connected to the second data output terminal, which is configured to receive the target clock signal and detect a metastable state of the first flip-flop unit according to the target clock signal. ### Claim 2 (depends on 1) The metastable state detection device according to claim 1, wherein both of the first flip-flop unit and the second flip-flop unit are D flip-flops. ### Claim 3 (depends on 1) The metastable state detection device according to claim 1, wherein the first flip-flop unit includes a first inverter and a first JK flip-flop, and a J terminal of the first JK flip-flop is connected to a K terminal of the first JK flip-flop via the first inverter; the second flip-flop unit includes a second inverter and a second JK flip-flop, and a J terminal of the second JK flip-flop is connected to a K terminal of the second JK flip-flop via the second inverter. ### Claim 4 (depends on 1) The metastable state detection device according to claim 1, wherein the processing module comprises: a reading unit connected to the second data output terminal, which is configured to read the target clock signal; a controller respectively connected to the reading unit and the delay unit, which is configured to detect the metastable state of the target clock signal, and obtain a calibration delay value for calibrating the metastable state according to the target clock signal, and is also configured to control the delay unit to delay the synchronization signal with the calibration delay value. ### Claim 5 An ADC circuit comprising: a metastable state detection device, wherein the metastable state detection device includes: a delay unit which is configured to receive a synchronization signal and delay the synchronization signal; a first flip-flop unit including a first clock input terminal, a first data input terminal and a first data output terminal, wherein the first clock input terminal is configured to receive a clock signal; the first data input terminal is connected to the delay unit and is configured to receive the delayed synchronization signal; a second flip-flop unit including a second clock input terminal, a second data input terminal and a second data output terminal, wherein the second clock input terminal is respectively connected to the delay unit and the first data input terminal and is configured to receive the delayed synchronization signal; the second data input terminal is connected to the first clock input terminal and is configured to receive a clock signal; the second data output terminal is configured to output a target clock signal that is synchronized with the delayed synchronization signal; a processing module connected to the second data output terminal, which is configured to receive the target clock signal and detect a metastable state of the first flip-flop unit according to the target clock signal. ### Claim 6 (depends on 5) The ADC circuit of claim 5, further comprising: a clock module which is configured to output a clock signal; a synchronization signal module which is configured to output a synchronization signal; wherein an input terminal of the delay unit is connected to the synchronization signal module, and an output terminal of the delay unit is respectively connected to the first data input terminal and the second clock terminal; the first clock input terminal, the second data input terminal and the first data output terminal are respectively connected to the clock generating module. ### Claim 7 (depends on 5) The ADC circuit of claim 5, wherein the clock module includes: a clock generating unit which is respectively connected to the first clock input terminal and the second data input terminal and is configured to generate the clock signal; a frequency dividing unit which is respectively connected to the clock generating unit and the first data output terminal, and is configured to perform a frequency dividing processing on the target synchronization signal output from the first flip-flop unit. ### Claim 8 A metastable detection method, wherein the detection method is applicable to a metastable state detection device, and wherein the metastable state detection device includes a delay unit, a first flip-flop unit, and a second flip-flop unit, wherein a clock input terminal of the first flip-flop unit is connected to a data input terminal of the second flip-flop unit, both of which are configured to receive a clock signal, and wherein a data input terminal of the first flip-flop unit and a clock input terminal of the second flip-flop unit are respectively connected to the delay unit, both of which are configured to receive a delayed synchronization signal; wherein the method includes: controlling the delay unit to delay the received synchronization signal based on preset delay values; recording target clock signals from the second flip-flop unit in correspondence with each of the delay values; detecting a metastable state of the first flip-flop unit according to the recorded correspondence relationships between the delay values and the target clock signals. ### Claim 9 (depends on 8) The metastable detection method according to claim 8, wherein detecting a metastable state of the first flip-flop unit according to the recorded correspondence relationships between the delay values and the target clock signals includes: when a rising edge or falling edge of the delayed synchronization signal being input to the second flip-flop unit as a triggering edge, obtaining a delay value within a setup/hold time window according to the recorded target clock signal; using the delay value within the setup/hold time window as the metastable state of the first flip-flop unit. ### Claim 10 (depends on 8) The metastable state detection method according to claim 8, wherein the method further comprises: calibrating the metastable state of the first flip-flop unit. ### Claim 11 (depends on 9) The metastable state detection method according to claim 9, wherein the calibrating the metastable state of the first flip-flop unit comprises: obtaining a delay value within a window where logic “1” is transitioned to logic “0” to the recorded target clock signal; taking the delay value within the window where logic “1” is transitioned to logic “0” as a calibration value; controlling the delay unit to delay the synchronization signal with the calibration value. ### Claim 12 (depends on 11) The metastable state detection method according to claim 11, wherein when there are a plurality of calibration values, a minimum calibration value of the plurality of calibration values is selected to be a target calibration value. ### Claim 13 (depends on 10) The metastable state detection method according to claim 10, wherein the method further comprises: detecting if a clock mode of the clock signal has been changed; when the clock mode has been changed, recalibrating the metastable state of the first flip-flop unit. ### Claim 14 (depends on 9) The metastable state detection method according to claim 9, wherein the method further comprises: detecting if a clock mode of the clock signal has been changed; when the clock mode has been changed, recalibrating the metastable state of the first flip-flop unit. ### Claim 15 (depends on 5) The ADC circuit according to claim 5, wherein both of the first flip-flop unit and the second flip-flop unit are D flip-flops. ### Claim 16 (depends on 5) The ADC circuit of according to claim 5, wherein the first flip-flop unit includes a first inverter and a first JK flip-flop, and a J terminal of the first JK flip-flop is connected to a K terminal of the first JK flip-flop via the first inverter; the second flip-flop unit includes a second inverter and a second JK flip-flop, and a J terminal of the second JK flip-flop is connected to a K terminal of the second JK flip-flop via the second inverter. ### Claim 17 (depends on 5) The ADC circuit of according to claim 5, wherein the processing module comprises: a reading unit connected to the second data output terminal, which is configured to read the target clock signal; a controller respectively connected to the reading unit and the delay unit, which is configured to detect the metastable state of the target clock signal, and obtain a calibration delay value for calibrating the metastable state according to the target clock signal, and is also configured to control the delay unit to delay the synchronization signal with the calibration delay value. ### Claim 18 (depends on 9) The metastable state detection method according to claim 9, wherein the method further comprises: calibrating the metastable state of the first flip-flop unit.