# US 11,451,234 B1 · Delay looked loop circuit and method of measuring delay

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- Number: US 11,451,234 B1
- Document ID: US11451234B1
- Status: Granted
- Kind: B1
- Application number: 17/534,384
- Filed: 2021-11-23
- Granted: 2022-09-20
- Earliest claimed: 2021-11-23
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: John Austin; Joseph Iadanza; Fran Keyser
- Web page: https://patentgrep.com/patent/US11451234B1

## CPC

- H03K 5/1534: Transition or edge detectors
- H03L 7/0812: {and where no voltage or current controlled oscillator is used}
- G01R 31/31725: {Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937)}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- H03L 7/085: concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A delay locked loop (DLL) circuit that includes a delay line, a pattern injecting circuit, a pattern detecting circuit and a counter is introduced. The delay line may align a phase of a reference clock signal with a phase of a feedback clock signal. The pattern injecting circuit injects a predetermined pattern to the reference clock signal to generate an injected reference clock signal and asserts the injected reference clock signal to the delay line. The pattern detecting circuit detects the predetermined pattern in the feedback clock signal. The counter determines a delay of the delay locked loop circuit according to a first timing when the injected reference clock signal is asserted to the delay line and a second timing when the predetermined pattern is detected in the feedback clock signal. A method of measuring a delay of the DLL circuit is also introduced.

## Claims

### Claim 1

A method of measuring a delay of a delay locked loop circuit, comprising:
asserting a reference clock signal to a delay line of the delay locked loop circuit, wherein the delay line is configured to align a phase of the reference clock signal with a phase of a feedback clock signal;
injecting a predetermined pattern to the reference clock signal to generate an injected reference clock signal;
asserting the injected reference clock signal to the delay line;
detecting the predetermined pattern in the feedback clock signal; and
determining the delay of the delay locked loop circuit according to a first timing when the injected reference clock signal is asserted to the delay line and a second timing when the predetermined pattern is detected in the feedback clock signal.

### Claim 2 (depends on 1)

The method of claim 1, wherein injecting the predetermined pattern to the reference clock signal to generate the injected reference clock signal comprising:
performing a logic operation to inject the predetermined pattern to the reference clock signal to generate the injected reference clock signal upon an assertion of a reset signal.

### Claim 3 (depends on 2)

The method of claim 2, wherein
the predetermined pattern includes a pulse that is held at a first logic state for at least one clock cycle of the reference clock signal.

### Claim 4 (depends on 2)

The method of claim 2, wherein
the predetermined pattern includes a pulse that is held at a second logic state for at least one clock cycle of the reference clock signal.

### Claim 5 (depends on 2)

The method of claim 2, wherein
the injected reference clock signal is asserted to the delay line after the phase of the reference clock signal is aligned with the phase of the feedback clock signal.

### Claim 6 (depends on 1)

The method of claim 1, wherein detecting the predetermined pattern in the feedback clock signal comprises:
detecting pulse edges of the reference clock signal and the pulse edges of the feedback clock signal;
determining a misalignment of the pulse edges of the reference clock signal and the pulse edges of the feedback clock signal; and
outputting a detection signal in response to detecting the misalignment of the pulse edges of the reference clock signal and the pulse edges of the feedback clock signal.

### Claim 7 (depends on 1)

The method of claim 1, wherein determining the delay of the delay locked loop circuit based on a time period from the first timing when the injected reference clock signal is supplied to the delay line and the second timing when the predetermined pattern is detected in the feedback clock signal comprises:
counting a number of clock cycles of the reference clock signal from the first timing to the second timing to obtain a count value; and
outputting the count value as the delay of the delay locked loop circuit.

### Claim 8 (depends on 7)

The method of claim 7, wherein counting the number of clock cycles of the reference clock signal from the first timing to the second timing comprising:
starting counting, by a counter of the delay locked loop circuit, at the first timing when the injected reference clock signal is asserted to the delay line; and
stopping counting, by the counter of the delay locked loop circuit, at the second timing when the predetermined pattern is detected in the feedback clock signal.

### Claim 9 (depends on 2)

The method of claim 2, further comprising:
delaying the reference clock signal to generate a delayed reference clock signal;
delaying the reset signal to generate a delayed reset signal, wherein
the predetermined pattern in the feedback clock signal is detected according to the delayed reference clock signal and the feedback clock signal, and
the delay of the delay locked loop circuit is determined according to the delayed reference clock signal and the delayed reset signal.

### Claim 10

A delay locked loop circuit, comprising:
a delay line, receiving a reference clock signal and generating a feedback clock signal, wherein the delay line is configured to align a phase of the reference clock signal with a phase of the feedback clock signal;
a pattern injecting circuit, coupled to the delay line, injecting a predetermined pattern to the reference clock signal to generate an injected reference clock signal, and asserting the injected reference clock signal to the delay line;
a pattern detecting circuit, coupled to the delay line, detecting the predetermined pattern in the feedback clock signal;
a counter, coupled to the pattern detecting circuit, determining a delay of the delay locked loop circuit according to a first timing when the injected reference clock signal is asserted to the delay line and a second timing when the predetermined pattern is detected in the feedback clock signal.

### Claim 11 (depends on 10)

The delay locked loop circuit of claim 10, wherein
the pattern injecting circuit comprises a logic circuit, and
the logic circuit is configured to perform a logic operation to inject the predetermined pattern to the reference clock signal to generate the injected reference clock signal upon an assertion of a reset signal to the logic circuit.

### Claim 12 (depends on 11)

The delay locked loop circuit of claim 11, wherein
the pattern detecting circuit detects the predetermined pattern in the feedback clock signal according to the reference clock signal, and
the counter determines the delay of the delay locked loop circuit according to the reference clock signal and the reset signal.

### Claim 13 (depends on 11)

The delay locked loop circuit of claim 11, wherein
the predetermined pattern is a pulse that is held at a first logic state for at least one clock cycle of the reference clock signal.

### Claim 14 (depends on 11)

The delay locked loop circuit of claim 11, wherein
the predetermined pattern is a pulse that is held at a second logic state for at least one clock cycle of the reference clock signal.

### Claim 15 (depends on 11)

The delay locked loop circuit of claim 11, wherein
the pattern injecting circuit is configured to assert the injected reference clock signal to the delay line after the phase of the reference clock signal is aligned with the phase of the feedback clock signal.

### Claim 16 (depends on 10)

The delay locked loop circuit of claim 10, wherein the pattern detecting circuit comprises an edge detection circuit that is configured to:
detect pulse edges of the reference clock signal and the pulse edges of the feedback clock signal;
determine a misalignment of the pulse edges of the reference clock signal and the pulse edges of the feedback clock signal; and
output a detection signal in response to detecting the misalignment of the pulse edges of the reference clock signal and the pulse edges of the feedback clock signal.

### Claim 17 (depends on 16)

The delay locked loop circuit of claim 16, wherein the counter comprises:
a stop signal generating circuit, coupled to the pattern detecting circuit, generating a stop signal according to the detection signal; and
a counter circuit, coupled to the stop signal generating circuit, counting a number of clock cycles of the reference clock signal from the first timing to the second timing to obtain a count value, and outputting the count value as the delay of the delay locked loop circuit.

### Claim 18 (depends on 17)

The delay locked loop circuit of claim 17, wherein
the counter circuit starts counting at the first timing when the injected reference clock signal is asserted to the delay line, and
the counter circuit stops counting at the second timing when the predetermined pattern is detected in the feedback clock signal.

### Claim 19 (depends on 11)

The delay locked loop circuit of claim 11, further comprising:
a signal generator, generating the reset signal, wherein the signal generator includes:
a first delay circuit, delaying the reference clock signal to generate a delayed reference clock signal; and
a second delay circuit, delaying the reset signal to generate a delayed reset signal.

### Claim 20 (depends on 19)

The delay locked loop circuit of claim 19, wherein
the pattern detecting circuit detects the predetermined pattern in the feedback clock signal according to the delayed reference clock signal, and
the counter determines the delay of the delay locked loop circuit according to the delayed reference clock signal and the delayed reset clock signal.