# US 11,451,232 B2 · Majority logic gate based flip-flop with non-linear polar material

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- Number: US 11,451,232 B2
- Document ID: US11451232B2
- Status: Granted
- Kind: B2
- Application number: 17/390,830
- Filed: 2021-07-30
- Published: 2022-06-23
- Granted: 2022-09-20
- Earliest claimed: 2020-12-21
- Assignees: Kepler Computing Inc.
- Applicants: Kepler Computing Inc.
- Inventors: Sasikanth Manipatruni; Yuan-Sheng Fang; Robert Menezes; Rajeev Kumar Dokania; Ramamoorthy Ramesh; Amrita Mathuriya
- Web page: https://patentgrep.com/patent/US11451232B2

## CPC

- H03K 19/23: Majority or minority circuits, i.e. giving output having the state of the majority or the minority of the inputs
- H03K 19/0008: {Arrangements for reducing power consumption}
- H03K 19/21: EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The sequential circuit includes a 3-input majority gate having first, second, and third inputs, and a first output. The sequential circuit includes a driver coupled to the first output, wherein the driver is to generate a second output. The sequential circuit further includes an exclusive-OR (XOR) gate to receive a clock and the second output, wherein the XOR gate is to generate a third output which couples to the second input, where the first input is to receive a data, and wherein the third input is to receive the second output.

## Claims

### Claim 1

An apparatus comprising:
a first latch comprising a first data input, a first data output, and a first clock input, wherein the first latch comprises a first 3-input majority gate having a first capacitor with non-linear polar material;
a second latch comprising a second data input, a second data output, and a second clock input, wherein the second latch comprises a second 3-input majority gate having a second capacitor with non-linear polar material, and wherein the first data output is coupled to the second data input; and
a logic gate coupled to the first clock input and the second clock input.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the first 3-input majority gate comprises first, second, and third non-ferroelectric capacitors to receive the first data input, a second input, and a third input, respectively.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the first 3-input majority gate comprises a non-linear polar capacitor to store a majority function output of the first data input, the second input, and the third input, and wherein one terminal of the non-linear polar capacitor provides an output of the first 3-input majority gate.

### Claim 4 (depends on 3)

The apparatus of claim 3, comprising:
a first transistor coupled to a first terminal of the non-linear polar capacitor, wherein the first transistor is controllable by a first signal;
a second transistor coupled to a second terminal of the non-linear polar capacitor, wherein the second transistor is controllable by a second signal; and
a third transistor coupled to the second terminal of the non-linear polar capacitor, wherein the third transistor is controllable by a third signal.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein the first transistor, the second transistor, and the third transistor are disabled in an evaluation phase, and enabled in a reset phase, wherein the reset phase is prior to the evaluation phase.

### Claim 6 (depends on 2)

The apparatus of claim 2, wherein the first latch comprises:
a driver coupled to an output of the first 3-input majority gate, wherein the driver is to generate an amplified output of the first 3-input majority gate, and wherein the amplified output is coupled to the third input.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein the first latch comprises:
a compare logic to receive the first clock input and the amplified output, wherein an output of the compare logic is coupled to the second input of the first 3-input majority gate.

### Claim 8 (depends on 6)

The apparatus of claim 6, wherein the driver comprises one of: a buffer, an amplifier, NAND, AND, OR, multiplexer, or NOR logic gates.

### Claim 9 (depends on 7)

The apparatus of claim 7, wherein the compare logic comprises an exclusive-OR (XOR) gate.

### Claim 10 (depends on 2)

The apparatus of claim 2, wherein the first, second, and third non-ferroelectric capacitors of the first 3-input majority gate comprise one of: metal-insulator-metal (MIM) capacitor, transistor gate capacitor, hybrid of metal and transistor capacitor; or
capacitor comprising paraelectric material.

### Claim 11 (depends on 1)

The apparatus of claim 1, wherein the logic gate is an inverting gate.

### Claim 12 (depends on 1)

The apparatus of claim 1, wherein the non-linear polar material includes one of:
ferroelectric material, paraelectric material, or non-linear dielectric material.

### Claim 13 (depends on 12)

The apparatus of claim 12, wherein the ferroelectric material includes one of:
Bismuth ferrite (BFO) with a doping material wherein the doping material is one of Lanthanum, or elements from lanthanide series of a periodic table;
Lead zirconium titanate (PZT), or PZT with a doping material, wherein the doping material is one of La or Nb;
a relaxor ferroelectric which includes one of lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), Barium Titanium-Bismuth Zinc Niobium Tantalum (BT-BZNT), or Barium Titanium-Barium Strontium Titanium (BT-BST);
perovskite ferroelectrics which include one of: BaTiO3, PbTiO3, KNbO3, or NaTaO3;
a hexagonal ferroelectric which includes one of: YmnO3 or LuFeO3;
hexagonal ferroelectrics which include one of a type h-RmnO3, where R is a rare earth element including one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium(Tm) , ytterbium (Yb), or yttrium (Y);
Hafnium (Hf), Zirconium (Zr), Aluminum (Al), Silicon (Si), their oxides or their alloyed oxides;
Hafnium oxides of a form, Ex Oy where E can be Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y;
Al(1-x)Sc(x)N, Ga(1-x)Sc(x)N, Al(1-x)Y(x)N or Al(1-x-y)Mg(x)Nb(y)N, y doped HfO2, where x includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y, wherein ‘x’ is a fraction;
Niobate type compounds LiNbO3, LiTaO3, Lithium iron Tantalum Oxy Fluoride, Barium Strontium Niobate, Sodium Barium Niobate, or Potassium strontium niobate; or
an improper ferroelectric which includes one of: [PTO/STO]n or [LAO/STO]n, where ‘n’ is between 1 to 100.

### Claim 14

An apparatus comprising:
a first latch comprising a first data input, a first data output, and a first clock input, wherein the first latch a first capacitor with non-linear polar material;
a second latch comprising a second data input, a second data output, and a second clock input, wherein the second latch comprises a second capacitor with non-linear polar material, and wherein the first data output is coupled to the second data input; and
an inverting logic gate coupled to the first clock input and the second clock input.

### Claim 15 (depends on 14)

The apparatus of claim 14, wherein the first latch comprises a first 3-input majority gate including the first capacitor, and wherein the second latch comprises a second 3-input majority gate including the second capacitor.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein the first 3-input majority gate comprises first, second, and third non-ferroelectric capacitors to receive the first data input, a second input, and a third input, respectively.

### Claim 17 (depends on 16)

The apparatus of claim 16, wherein the first capacitor to store a majority function output of the first data input, the second input, and the third input, wherein one terminal of the first capacitor provides an output of the first 3-input majority gate, wherein the apparatus comprises:
a driver coupled to the output of the first 3-input majority gate, wherein the driver is to generate an amplified output of the first 3-input majority gate, and wherein the amplified output is coupled to the third input; and
a compare logic to receive the first clock input and the amplified output, wherein an output of the compare logic is coupled to the second input of the first 3-input majority gate.

### Claim 18

A system comprising:
a processor circuitry to execute one or more instructions;
a communication interface communicatively coupled to the processor circuitry; and
a memory coupled to the processor circuitry, wherein the memory is to store the one or more instructions, and wherein the processor circuitry comprises a flip-flop which includes:
a first latch comprising a first data input, a first data output, and a first clock input, wherein the first latch a first capacitor with non-linear polar material;
a second latch comprising a second data input, a second data output, and a second clock input, wherein the second latch comprises a second capacitor with non-linear polar material, and wherein the first data output is coupled to the second data input; and
an inverting logic gate coupled to the first clock input and the second clock input.

### Claim 19 (depends on 18)

The system of claim 18, wherein the first latch comprises a first 3-input majority gate including the first capacitor, and wherein the second latch comprises a second 3-input majority gate including the second capacitor.

### Claim 20 (depends on 19)

The system of claim 19, wherein the first 3-input majority gate comprises first, second, and third non-ferroelectric capacitors to receive the first data input, a second input, and a third input, respectively.