# US 11,451,230 B2 · Compute dataflow architecture > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,451,230 B2 - Document ID: US11451230B2 - Status: Granted - Kind: B2 - Application number: 16/857,090 - Filed: 2020-04-23 - Published: 2021-10-28 - Granted: 2022-09-20 - Earliest claimed: 2020-04-23 - Assignees: Xilinx, Inc. - Applicants: Xilinx, Inc. - Inventors: Steven P. Young; Brian C. Gaide - Web page: https://patentgrep.com/patent/US11451230B2 ## CPC - H03K 19/17744: {for input/output signals} - H03K 19/17748: Structural details of configuration resources - G06F 1/10: Distribution of clock signals {, e.g. skew} - G06F 8/40: Transformation of program code - H03K 19/17736: Structural details of routing resources - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An example integrated circuit includes an array of circuit tiles; interconnect coupling the circuit tiles in the array, the interconnect including interconnect tiles each having a plurality of connections that include at least a connection to a respective one of the circuit tiles and a connection to at least one other interconnect tile; and a plurality of local crossbars in each of the interconnect tiles, the plurality of local crossbars coupled to form a non-blocking crossbar, each of the plurality of local crossbars including handshaking circuitry for asynchronous communication. ## Claims ### Claim 1 An integrated circuit, comprising: an array of circuit tiles comprising circuitry configured to perform a data operation; an interconnect coupling the circuit tiles in the array, the interconnect including interconnect tiles each having a plurality of connections that include at least a first connection to a respective one of the circuit tiles and multiple connections to multiple other interconnect tiles; and a plurality of local crossbars in each of the interconnect tiles, the plurality of local crossbars coupled to form a non-blocking crossbar, wherein the non-blocking crossbar is configured to simultaneously route a first signal and a second signal of a plurality of received signals, wherein, each of the plurality of local crossbars comprises handshaking circuitry for asynchronous communication between inputs of the local crossbar and outputs of the local crossbar. ### Claim 2 (depends on 1) The integrated circuit of claim 1, wherein the plurality of connections of each interconnect tile includes north, east, south, and west connections to respective north, east, south, and west interconnect tiles. ### Claim 3 (depends on 1) The integrated circuit of claim 1, wherein the plurality of connections of each interconnect tile includes a connection to an adjacent interconnect tile and a connection to a non-adjacent interconnect tile. ### Claim 4 (depends on 1) The integrated circuit of claim 1, wherein the plurality of local crossbars are configured to remove connections that reverse direction through the non-blocking crossbar. ### Claim 5 (depends on 1) The integrated circuit of claim 1, wherein the plurality of local crossbars are configured to route all combinations of signals through the local crossbars but only to arbitrary output pins rather than all output pin permutations. ### Claim 6 (depends on 1) The integrated circuit of claim 1, wherein the handshaking circuitry permits fan out in each of the plurality of local crossbars where one input signal can be outputted on multiple outputs of a local crossbar simultaneously. ### Claim 7 (depends on 1) The integrated circuit of claim 1, wherein the array of circuit tiles comprise programmable logic of the integrated circuit. ### Claim 8 (depends on 1) The integrated circuit of claim 1, further comprising: configuration memory configured to program the array of circuit tiles and the interconnect. ### Claim 9 An integrated circuit, comprising: an array of circuit tiles comprising circuitry configured to perform a data operation; and an interconnect coupling the circuit tiles in the array, the interconnect including interconnect tiles each having a plurality of connections that include at least a first connection to a respective one of the circuit tiles and multiple connections to multiple other interconnect tiles, and wherein the interconnect tiles are connected to each other using a plurality of buses, wherein each of the interconnect tiles comprises a local crossbar including handshaking circuitry for asynchronous communication, wherein the handshaking circuitry is configured to perform asynchronous handshaking so that one input signal to the local crossbar can fan-out to be output simultaneously at multiple outputs of the local crossbar. ### Claim 10 (depends on 9) The integrated circuit of claim 9, wherein the plurality of connections of each interconnect tile includes north, east, south, and west connections to respective north, east, south, and west interconnect tiles. ### Claim 11 (depends on 9) The integrated circuit of claim 9, wherein the plurality of connections of each interconnect tile includes a connection to an adjacent interconnect tile and a connection to a non-adjacent interconnect tile. ### Claim 12 (depends on 9) The integrated circuit of claim 9, wherein the local crossbars are configured to remove connections that reverse direction through a non-blocking crossbar. ### Claim 13 (depends on 9) The integrated circuit of claim 9, wherein the local crossbars are configured to route all combinations of signals through the local crossbars but only to arbitrary output pins rather than all output pin permutations. ### Claim 14 (depends on 9) The integrated circuit of claim 9, wherein the array of circuit tiles comprises programmable logic of the integrated circuit. ### Claim 15 (depends on 9) The integrated circuit of claim 9, further comprising: configuration memory configured to program the array of circuit tiles and the interconnect. ### Claim 16 (depends on 9) The integrated circuit of claim 9, wherein the handshaking circuitry includes a plurality of acknowledge signals for a plurality of data signals in a data path. ### Claim 17 (depends on 9) The integrated circuit of claim 9, wherein one input signal can be outputted on multiple outputs of a local crossbar simultaneously. ### Claim 18 (depends on 17) The integrated circuit of claim 17, wherein the handshaking circuitry determines the one input signal is received at at least two outputs of the multiple outputs. ### Claim 19 (depends on 9) The integrated circuit of claim 9, wherein the fan-out is localized.