# US 11,451,229 B1 · Application specific integrated circuit accelerators > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,451,229 B1 - Document ID: US11451229B1 - Status: Granted - Kind: B1 - Application number: 17/135,607 - Filed: 2020-12-28 - Granted: 2022-09-20 - Earliest claimed: 2017-07-21 - Assignees: Google Inc. - Applicants: Google LLC - Inventors: Michial Allen Gunter; Charles Henry Leichner, IV; Tammo Spalink - Web page: https://patentgrep.com/patent/US11451229B1 ## CPC - H03K 19/17744: {for input/output signals} - G06N 3/0464: Convolutional networks [CNN, ConvNet] - G06N 3/063: using electronic means - G06N 3/082: modifying the architecture, e.g. adding, deleting or silencing nodes or connections - H03K 19/1774: {for global signals, e.g. clock, reset} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS ## Abstract A tile including circuitry for use with machine learning models, the tile including: a first computational array of cells, in which the computational array of cells is a sub-array of a larger second computational array of cells; local memory coupled to the first computational array of cells; and multiple controllable bus lines, in which a first subset of the multiple controllable bus lines include multiple general purpose controllable bus lines couplable to the local memory. ## Claims ### Claim 1 An apparatus for use with machine learning models, the apparatus comprising: an arithmetic computational circuit, wherein the arithmetic computational circuit comprises a first array of cells configured to perform mathematical operations; memory; a plurality of switchable bus lines comprising a first switchable bus line subset and a second switchable bus line subset, wherein the first switchable bus line subset is configured to control whether data is transferred between the first switchable bus line subset and the memory along a first dimension and whether data is transferred between the first switchable bus line subset and the arithmetic computational circuit along the first dimension, wherein the second switchable bus line subset is configured to control whether data is transferred along a second dimension that is orthogonal to the first dimension, wherein the first switchable bus line subset comprises at least one control element positioned proximate to a first memory circuit of the memory and to the first array of cells, wherein the at least one control element of the first switchable bus line subset is configured to control whether data is transferred between the first switchable bus line subset and the first memory circuit and whether data is transferred between the first switchable bus line subset and the first array of cells. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the arithmetic computational circuit comprises a plurality of array of cells arranged in a grid that extends along the first dimension and along the second dimension, wherein the plurality of array of cells comprises the first array of cells. ### Claim 3 (depends on 2) The apparatus of claim 2 comprising a vector processing unit, wherein a first half of the plurality of array of cells is arranged on a first side of the vector processing unit, and wherein a second half of the plurality of array of cells is arranged on a second side of the vector processing unit that is opposite to the first side of the vector processing unit. ### Claim 4 (depends on 2) The apparatus of claim 2, wherein the memory comprises a plurality of memory circuits including the first memory circuit, wherein each memory circuit of the plurality of memory circuits is positioned proximate to a different corresponding array of cells from the plurality of array of cells, and the first memory circuit is positioned proximate to the first array of cells. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein each memory circuit of the plurality of memory circuits comprises SRAM. ### Claim 6 (depends on 4) The apparatus of claim 4, wherein the second switchable bus line subset comprises at least one control element positioned proximate to the first memory circuit and to the first array of cells, wherein the at least one control element of the second switchable bus line subset is configured to control whether data is transferred with an adjacent control element of the second switchable bus line subset, wherein the adjacent control element is positioned proximate to a second memory circuit and a second array of cells. ### Claim 7 (depends on 4) The apparatus of claim 4, wherein the at least one control element of the first switchable bus line subset comprises a flip-flop. ### Claim 8 (depends on 4) The apparatus of claim 4, wherein the at least one control element of the first switchable bus line subset comprises a multiplexor. ### Claim 9 (depends on 2) The apparatus of claim 2, wherein the plurality of switchable bus lines are configured to transfer data from the first array of cells along the first dimension, along the second dimension, or along both the first dimension and the second dimension to a second array of cells of the plurality of array of cells, wherein the second array of cells is non-adjacent to the first array of cells in the grid. ### Claim 10 (depends on 1) The apparatus of claim 1, wherein the first array of cells is configured to perform multiply and accumulate operations. ### Claim 11 (depends on 1) The apparatus of claim 1, wherein the plurality of switchable bus lines are configured to change a direction of data movement along the plurality of switchable bus lines between the first dimension and the second dimension. ### Claim 12 An apparatus for use with machine learning models, the apparatus comprising: an arithmetic computational circuit, wherein the arithmetic computational circuit comprises a first array of cells configured to perform mathematical operations; memory; a plurality of switchable bus lines comprising a first switchable bus line subset and a second switchable bus line subset, wherein the first switchable bus line subset is configured to control whether data is transferred between the first switchable bus line subset and the memory along a first dimension and whether data is transferred between the first switchable bus line subset and the arithmetic computational circuit along the first dimension, wherein the second switchable bus line subset is configured to control whether data is transferred along a second dimension that is orthogonal to the first dimension; and a vector processing unit, wherein a first half of the first array of cells is arranged on a first side of the vector processing unit, and wherein a second half of the first array of cells is arranged on a second side of the vector processing unit that is opposite to the first side of the vector processing unit.