# US 11,451,224 B2 · Single-pole double-throw switch circuit with type-c interface, analog switch chip, and electronic device

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- Number: US 11,451,224 B2
- Document ID: US11451224B2
- Status: Granted
- Kind: B2
- Application number: 17/280,907
- Filed: 2020-08-10
- Published: 2022-06-09
- Granted: 2022-09-20
- Earliest claimed: 2019-08-28
- Assignees: Shanghai Yaohuo Microelectronics Co., Ltd.
- Applicants: SHANGHAI YAOHUO MICROELECTRONICS Co., Ltd.
- Inventors: Hongxia Tao
- Web page: https://patentgrep.com/patent/US11451224B2

## CPC

- H03K 17/567: Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
- H03K 17/693: Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00)
- G06F 17/00: Digital computing or data processing equipment or methods, specially adapted for specific functions (information retrieval, database structures or file system structures therefor G06F16/00)
- H03K 2017/515: {Mechanical switches; Electronic switches controlling mechanical switches, e.g. relais}
- H03K 2217/0018: Special modifications or use of the back gate voltage of a FET
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

The present invention provides a single-pole double-throw switch circuit with a Type-C interface, an analog switch chip and an electronic device, which can generate a reverse bias voltage across a first diode, so that a capacitance value of a PN junction can be significantly reduced after the reverse bias voltage is applied to the PN junction. Further, a ground capacitance corresponding to a COM point when the first diode is turned off can be effectively reduced, avoiding the reduction of a bandwidth of a digital path due to excessive capacitance. It can be seen that the present invention can realize a large size of a first field effect transistor and a high bandwidth of the digital path simultaneously, thereby facilitating the simultaneous improvement of the THD performance of an analog audio path and the bandwidth of the digital path, and avoiding conflicts between the two.

## Claims

### Claim 1

A single-pole double-throw switch circuit with a Type-C interface, comprising a digital path and an analog audio path that are configured to be turned on in a time-multiplexed manner and are connected to the same COM port, wherein:
two pins of the COM port are connected to a D+ pin and a D− pin of the Type-C interface respectively;
the analog audio path is provided with a first field effect transistor, the analog audio path being through a source of the first field effect transistor and a drain of the first field effect transistor;
a PN junction between a substrate of the first field effect transistor and the source of the first field effect transistor forms a first diode;
the substrate of the first field effect transistor is a first terminal of the first diode, and the source of the first field effect transistor is a second terminal of the first diode;
the single-pole double-throw switch circuit with a Type-C interface further comprises a reverse bias voltage module; and
the reverse bias voltage module is connected between the first terminal and the second terminal of the first diode for generating a reverse bias voltage across the first diode.

### Claim 2 (depends on 1)

The circuit according to claim 1, wherein the reverse bias voltage module comprises an isolation field effect transistor, a voltage adjustment unit, and an impedance unit capable of generating a voltage drop when a current flows; a source of the isolation field effect transistor is connected to one terminal of the impedance unit;
a gate of the isolation field effect transistor and the second terminal of the first diode are commonly connected to a first node; the other terminal of the impedance unit and the first terminal of the first diode are commonly connected to a second node;
when the reverse bias voltage is generated, a potential of the first node is higher than a potential of the second node, and a voltage between the first node and the second node is the reverse bias voltage; and
the voltage adjustment unit is connected to the second node for adjusting the reverse bias voltage, so that the reverse bias voltage is at a required value or within a required value range.

### Claim 3 (depends on 2)

The circuit according to claim 2, wherein the voltage adjustment unit comprises a current determination device connected to the second node; and
the current determination device is configured to determine a current magnitude of the second node, so that the reverse bias voltage is maintained at the required value or within the required value range.

### Claim 4 (depends on 3)

The circuit according to claim 3, wherein the current determination device comprises a current source connected to the second node.

### Claim 5 (depends on 2)

The circuit according to claim 2, wherein the impedance unit comprises a resistor connected in series between the source of the isolation field effect transistor and the second node.

### Claim 6 (depends on 2)

The circuit according to claim 2, wherein the voltage adjustment unit comprises a variable voltage source provided between the second node and a third node, a potential of the third node being lower than the potential of the second node, the variable voltage source is configured to determine a voltage between the third node and the second node, so that the reverse bias voltage is maintained at a required value or be within a required value range.

### Claim 7 (depends on 1)

The circuit according to claim 1, wherein the value range of the reverse bias voltage is 4V to 5V.

### Claim 8 (depends on 1)

The circuit according to claim 1, wherein the digital path is provided with a second field effect transistor, and the PN junction between the substrate and the source of the second field effect transistor forms a second diode.

### Claim 9 (depends on 2)

The circuit according to claim 2, wherein the digital path is provided with a second field effect transistor, and the PN junction between the substrate and the source of the second field effect transistor forms a second diode.

### Claim 10 (depends on 3)

The circuit according to claim 3, wherein the digital path is provided with a second field effect transistor, and the PN junction between the substrate and the source of the second field effect transistor forms a second diode.

### Claim 11 (depends on 4)

The circuit according to claim 4, wherein the digital path is provided with a second field effect transistor, and the PN junction between the substrate and the source of the second field effect transistor forms a second diode.

### Claim 12 (depends on 5)

The circuit according to claim 5, wherein the digital path is provided with a second field effect transistor, and the PN junction between the substrate and the source of the second field effect transistor forms a second diode.

### Claim 13 (depends on 6)

The circuit according to claim 6, wherein the digital path is provided with a second field effect transistor, and the PN junction between the substrate and the source of the second field effect transistor forms a second diode.

### Claim 14

A circuit comprising:
a single-pole double-throw switch circuit with a Type-C interface, the single-pole double-throw switch circuit comprising:
a digital path and an analog path, the digital path and the analog path being connected to a same COM port, the single-pole double-throw switch circuit being configured to time-multiplex the digital path and the analog path, wherein the analog path includes a first field effect transistor, the analog path being through a source of the first field effect transistor and a drain of the first field effect transistor, a PN junction being formed between a substrate of the first field effect transistor and the source of the first field effect transistor; and
a reverse bias voltage circuit connected between the substrate of the first field effect transistor and the source of the first field effect transistor, the reverse bias voltage circuit being configured to generate a reverse bias voltage across the PN junction.

### Claim 15 (depends on 14)

The circuit according to claim 14, wherein the reverse bias voltage circuit comprises:
an isolation field effect transistor;
a voltage adjustment unit; and
an impedance unit capable of generating a voltage drop; and wherein:
a source of the isolation field effect transistor is connected to a terminal of the impedance unit;
a gate of the isolation field effect transistor is connected to and the source of the first field effect transistor;
another terminal of the impedance unit is connected to the substrate of the first field effect transistor;
when the reverse bias voltage is generated, a potential of the source of the first field effect transistor is higher than a potential of the substrate of the first field effect transistor, and a voltage between the source and the substrate of the first field effect transistor is the reverse bias voltage; and
the voltage adjustment unit is connected to the substrate of the first field effect transistor for adjusting the reverse bias voltage, so that the reverse bias voltage is at a required value or within a required value range.

### Claim 16 (depends on 15)

The circuit according to claim 15, wherein the voltage adjustment unit comprises a current determination device connected to the substrate of the first field effect transistor, wherein the current determination device is configured to determine a current magnitude at the substrate of the first field effect transistor, so that the reverse bias voltage is maintained at the required value or within the required value range.

### Claim 17 (depends on 16)

The circuit according to claim 16, wherein the current determination device comprises a current source connected to the substrate of the first field effect transistor.

### Claim 18 (depends on 15)

The circuit according to claim 15, wherein the impedance unit comprises a resistor connected in series between the source of the isolation field effect transistor and the substrate of the first field effect transistor.

### Claim 19 (depends on 15)

The circuit according to claim 15, wherein the voltage adjustment unit comprises a variable voltage source provided between the substrate of the first field effect transistor and a node, a potential of the node is lower than the potential of the substrate of the first field effect transistor, the variable voltage source is configured to determine a voltage between the node and the substrate of the first field effect transistor, so that the reverse bias voltage is maintained at a required value or within a required value range.

### Claim 20 (depends on 14)

The circuit according to claim 14, wherein the digital path includes a second field effect transistor, the digital path being through a source of the second field effect transistor and a drain of the second field effect transistor.