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US 11,451,219 B2Granted
Delay circuit and delay structure
AssigneeChangxin Memory Technologies, Inc.
InventorsWeibing Shang, Anping Qiu, Chan Chen, Kangling Ji
Life of this patent
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Abstract
A delay circuit and a delay structure are provided. The circuit includes: a first delay unit configured to delay a rising edge and/or a falling edge of a pulse signal, where, an input terminal of the first delay unit receives the pulse signal, and an output terminal of the first delay unit outputs a first delay signal, and a second delay unit, configured to delay the first delay signal, where an input terminal of the second delay unit is connected to the output terminal of the first delay unit, and an output terminal of the second delay unit outputs a second delay signal.
Claims19
A delay circuit, comprising:
- a first delay circuit, configured to delay at least one of a rising edge or falling edge of a pulse signal, wherein an input terminal of the first delay circuit receives the pulse signal, and an output terminal of the first delay circuit outputs a first delay signal;
- a second delay circuit, configured to delay the first delay signal, wherein an input terminal of the second delay circuit is connected to the output terminal of the first delay circuit, and an output terminal of the second delay circuit outputs a second delay signal;
- and
- a feedback loop, wherein a first terminal of the feedback loop is connected to the output terminal of the second delay circuit, and a second terminal of the feedback loop is connected to the input terminal of the second delay circuit, wherein the feedback loop is configured to reduce a time for the first delay signal from a level shift point to a low level or a time for the first delay signal from a level shift point to a high level,
- wherein a delay time between a rising edge of the second delay signal and the rising edge of the pulse signal is denoted as a rising edge delay time;
- a delay time between a falling edge of the second delay signal and the falling edge of the pulse signal is denoted as a falling edge delay time;
- a variation value, varying with a first parameter, of at least one of the rising edge delay time or the falling edge delay time is within a first range, and the first parameter comprises at least one of the following:
- manufacturing process, power supply voltage wave, or working temperate of the delay circuit.
5 more elements
A delay structure, comprising:
- a plurality of delay circuits connected in series, wherein each of the plurality of delay circuits comprises:
- a first delay circuit, configured to delay at least one of a rising edge or falling edge of a pulse signal, wherein an input terminal of the first delay circuit receives the pulse signal, and an output terminal of the first delay circuit outputs a first delay signal;
- a second delay circuit, configured to delay the first delay signal, wherein an input terminal of the second delay circuit is connected to the output terminal of the first delay circuit, and an output terminal of the second delay circuit outputs a second delay signal;
- and
- a feedback loop, wherein a first terminal of the feedback loop is connected to the output terminal of the second delay circuit, and a second terminal of the feedback loop is connected to the input terminal of the second delay circuit, wherein the feedback loop is configured to reduce a time for the first delay signal from a level shift point to a low level or a time for the first delay signal from a level shift point to a high level,
- wherein a delay time between a rising edge of the second delay signal and the rising edge of the pulse signal is denoted as a rising edge delay time;
- a delay time between a falling edge of the second delay signal and the falling edge of the pulse signal is denoted as a falling edge delay time;
- a variation value, varying with a first parameter, of at least one of the rising edge delay time or the falling edge delay time is within a first range, and the first parameter comprises at least one of the following:
- manufacturing process, power supply voltage wave, or working temperate of the delay circuit;
- wherein an input terminal of a first one of the delay circuits receives the pulse signal, an output terminal of an (M−1)th one of the delay circuits is connected to an input terminal of an Mth one of the delay circuits, and an output terminal of the Mth one of the delay circuits outputs a delay signal with a preset delay time, wherein M is an integer greater than or equal to 2.
7 more elements
Dependencies are inferred from the claim text.