# US 11,451,199 B2 · Power amplifier systems with control interface and bias circuit

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- Number: US 11,451,199 B2
- Document ID: US11451199B2
- Status: Granted
- Kind: B2
- Application number: 16/943,336
- Filed: 2020-07-30
- Published: 2021-02-18
- Granted: 2022-09-20
- Earliest claimed: 2012-06-14
- Assignees: Skyworks Solutions, Inc.
- Applicants: Skyworks Solutions, Inc.
- Inventors: David Steven Ripley; Philip John Lehtola; Peter J. Zampardi, Jr.; Hongxiao Shao; Tin Myint Ko; Matthew Thomas Ozalas
- Web page: https://patentgrep.com/patent/US11451199B2

## CPC

- H03F 3/213: in integrated circuits
- H03F 1/0205: {in transistor amplifiers}
- H03F 3/19: with semiconductor devices only
- H03F 3/195: in integrated circuits
- H03F 3/21: with semiconductor devices only {(H03F3/245 takes precedence)}
- H03F 3/245: {with semiconductor devices only}
- H03F 3/60: Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators (H03F3/54 takes precedence)
- H10D 10/021: {of heterojunction BJTs [HBT]}
- H10D 10/821: {Vertical heterojunction BJTs}
- H10D 30/87: FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET] {(FETs having Schottky contact on top of heterojunction gate H10D30/801)}
- H10D 62/137: {Collector regions of BJTs}
- H10D 62/138: {Pedestal collectors}
- H10D 62/60: Impurity distributions or concentrations
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 62/85: being Group III-V materials, e.g. GaAs
- H10D 84/01: Manufacture or treatment
- H10D 84/0107: {Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs}
- H10D 84/0109: {the at least one component covered by H10D12/00 or H10D30/00 being a MOS device}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/05: using Group III-V technology
- H10D 84/401: {Combinations of FETs or IGBTs with BJTs}
- H10D 88/01: {Manufacture or treatment}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 42/276: {the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation}
- H10W 44/20: at high-frequency [HF] or radio frequency [RF]
- H10W 70/092: {Adapting interconnections, e.g. making engineering changes, repairing}
- H10W 70/097: {Cleaning}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/479: {on or in insulating or insulated package substrates, interposers, or redistribution layers}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/658: {for devices provided for in groups H10D8/00 - H10D48/00}
- H10W 70/66: Conductive materials thereof
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/0198: {batch processes}
- H10W 74/016: {using moulds}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H03F 1/565: {using inductive elements}
- H03F 3/187: in integrated circuits
- H03F 3/347: in integrated circuits
- H03F 3/45: Differential amplifiers (differential sense amplifiers G11C7/062)
- H03F 2200/387: A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
- H03F 2200/451: the amplifier being a radio frequency amplifier
- H03F 2200/48: the output of the amplifier being coupled out by a capacitor
- H03F 2200/555: A voltage generating circuit being realised for biasing different circuit elements
- H10D 1/43: Resistors having PN junctions
- H10D 10/80: Heterojunction BJTs
- H10D 30/0612: {of lateral single-gate Schottky FETs}
- H10D 62/124: {Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions}
- H10D 62/177: {Base regions of bipolar transistors, e.g. BJTs or IGBTs}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10W 44/206: {Wires}
- H10W 44/209: {Vertical interconnections, e.g. vias}
- H10W 44/226: {for HF amplifiers}
- H10W 44/231: {Arrangements for applying bias}
- H10W 44/234: {Arrangements for impedance matching}
- H10W 70/69: Insulating materials thereof
- H10W 72/075: {of bond wires}
- H10W 72/07533: {Ultrasonic bonding, e.g. thermosonic bonding}
- H10W 72/07552: {changes in structures or sizes}
- H10W 72/527: {Multiple bond wires having different sizes}
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/5475: {multiple bond wires connected to common bond pads at both ends of the wires}
- H10W 72/552: {comprising metals or metalloids, e.g. silver}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/5525: {comprising copper [Cu]}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/755: {between a chip and a laterally-adjacent insulating package substrate, interpose or RDL}
- H03F: AMPLIFIERS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

One aspect of this disclosure is a power amplifier system that includes a control interface, a power amplifier, a passive component, and a bias circuit. The power amplifier and the passive component can be on a first die. The bias circuit can be on a second die. The control interface can operate as a serial interface or as a general purpose input/output interface. The power amplifier can be controllable based at least partly on an output signal from the control interface. The bias circuit can generate a bias signal based at least partly on an indication of the electrical property of the passive component. Other embodiments of the system are provided along with related methods and components thereof.

## Claims

### Claim 1

A power amplifier system comprising:
a control interface configured to receive an input signal, operate as a serial interface in response to the input signal having a first value, operate as a general purpose input/output interface in response to the input signal having a second value, and provide an output signal;
a power amplifier configured to amplify a radio frequency signal, the power amplifier controllable based at least partly on the output signal;
a passive component having an electrical property that depends on a condition of a die that includes the passive component and the power amplifier; and
a bias circuit included on a different die than the power amplifier, the bias circuit configured to generate a bias signal based at least partly on an indication of the electrical property of the passive component.

### Claim 2 (depends on 1)

The power amplifier system of claim 1 wherein the control interface is configured to set a mode of the power amplifier.

### Claim 3 (depends on 1)

The power amplifier system of claim 1 wherein the passive component includes a resistor and the electrical property is a resistance.

### Claim 4 (depends on 1)

The power amplifier system of claim 1 wherein the power amplifier includes a heterojunction bipolar transistor, and the passive component includes a semiconductor resistor having a resistive layer formed of a material that is substantially the same as a material of a layer of the heterojunction bipolar transistor.

### Claim 5 (depends on 4)

The power amplifier system of claim 4 wherein an emitter of the heterojunction bipolar transistor includes the layer.

### Claim 6 (depends on 4)

The power amplifier system of claim 4 wherein a base of the heterojunction bipolar transistor includes the layer.

### Claim 7 (depends on 1)

The power amplifier system of claim 1 wherein the condition of the die is temperature of the die.

### Claim 8 (depends on 1)

The power amplifier system of claim 1 wherein the condition of the die is a process variation associated with the die.

### Claim 9 (depends on 1)

The power amplifier system of claim 1 wherein the condition of the die is a beta parameter associated with the die.

### Claim 10 (depends on 1)

The power amplifier system of claim 1 wherein the input signal is a voltage input/output signal.

### Claim 11 (depends on 10)

The power amplifier system of claim 10 wherein the control interface is configured to receive the voltage input/output signal at a single voltage input/output pin.

### Claim 12 (depends on 1)

The power amplifier system of claim 1 wherein the control interface includes a tri-state buffer operable in a first state for reading data from the serial interface and operable in a second state for writing data to the serial interface.

### Claim 13 (depends on 1)

The power amplifier system of claim 1 wherein the control interface includes a combinational logic block and a level shifter, the combinational logic block is configured to provide a signal to the level shifter, and the level shifter is configured to provide the output signal.

### Claim 14

A power amplifier system comprising:
a digital control interface configured to receive a voltage input/output signal at a voltage/input output pin, operate as a serial interface in response to the voltage input/output signal having a first logic value, operate as a general purpose input/output interface in response to the voltage input/output signal having a second logic value, and provide an output signal;
a power amplifier that is controllable based at least partly on the output signal;
a resistor having a resistance that depends on a condition of a die that includes the resistor and the power amplifier; and
a bias circuit included on a different die than the power amplifier, the bias circuit configured to generate a bias signal based at least partly on an indication of the resistance of the resistor.

### Claim 15 (depends on 14)

The power amplifier system of claim 14 wherein the power amplifier includes a heterojunction bipolar transistor, and the resistor includes a resistive layer formed of a material that is substantially the same as a material of a layer of the heterojunction bipolar transistor.

### Claim 16 (depends on 14)

The power amplifier system of claim 14 wherein the digital control interface includes a combinational logic block and a level shifter, the combinational logic block is configured to provide a signal to the level shifter, and the level shifter is configured to provide the output signal.

### Claim 17

A power amplifier system comprising:
a power amplifier configured to amplify a radio frequency signal;
a control interface including a serial interface and a general purpose input/output interface, the control interface configured to set a mode of the power amplifier;
a passive component having an electrical property that depends on a condition of a die that includes the passive component and the power amplifier; and
a bias circuit included on a different die than the power amplifier, the bias circuit configured to generate a bias signal based at least partly on an indication of the electrical property of the passive component.

### Claim 18 (depends on 17)

The power amplifier system of claim 17 wherein the passive component is a semiconductor resistor.

### Claim 19 (depends on 17)

The power amplifier system of claim 17 wherein the control interface is configured to receive a voltage input/output signal and activate the general purpose input/output interface based on a signal level of the voltage input/output signal.

### Claim 20 (depends on 18)

The power amplifier system of claim 18 wherein the power amplifier includes a heterojunction bipolar transistor, and the semiconductor resistor has a resistive layer formed of a material that is substantially the same as a material of a layer of the heterojunction bipolar transistor.