Processing and storage circuit

A processing and storage circuit, comprising:

• an internal bus;
• at least one first-level internal memory unit, coupled to the internal bus;
• at least one central processing unit (CPU), coupled to the at least one first-level internal memory unit via the internal bus, comprising a second-level internal memory unit, wherein the CPU is configured to access the first-level internal memory unit and the second-level internal memory unit, and wherein when the CPU accesses data, the first-level internal memory unit is accessed preferentially;
• at least one hardware acceleration engine, coupled to the at least one first-level internal memory unit via the internal bus, configured to access the first-level internal memory unit;
• and
• an arbiter, coupled to the internal bus, configured to decide whether the CPU or the hardware acceleration engine be allowed to access the at least one first-level internal memory unit;
• wherein the arbiter sets the priority of the CPU accessing the first-level internal memory unit to be over the hardware acceleration engine, wherein the CPU further comprises:
• a core circuit;
• a first-level control circuit, coupled to the core circuit and the internal bus, wherein the core circuit access the first-level internal memory unit through the first-level control circuit;
• a first-level cache unit, coupled to the first-level control circuit, so that the core circuit accesses the first-level cache unit through the first-level control circuit;
• a second-level control circuit, coupled to the first-level control circuit;
• the second-level internal memory unit, coupled to the second-level control circuit, so that the core circuit accesses the second-level internal memory unit through the second-level control circuit;
• a second-level cache unit, coupled to the second-level control circuit, so that the core circuit accesses the second-level cache unit through the second-level control circuit;
• and
• a bus interface unit, coupled to the first-level control circuit, the second-level control circuit, and the external bus.

A processing and storage circuit, comprising:

• an internal bus;
• at least one first-level internal memory unit, coupled to the internal bus;
• at least one central processing unit (CPU), coupled to the at least one first-level internal memory unit via the internal bus, comprising a second-level internal memory unit, wherein the CPU is configured to access the first-level internal memory unit and the second-level internal memory unit, and wherein when the CPU accesses data, the first-level internal memory unit is accessed preferentially;
• at least one hardware acceleration engine, coupled to the at least one first-level internal memory unit via the internal bus, configured to access the first-level internal memory unit;
• and
• an arbiter, coupled to the internal bus, configured to decide whether the CPU or the hardware acceleration engine be allowed to access the at least one first-level internal memory unit;
• wherein the arbiter sets the priority of the CPU accessing the first-level internal memory unit to be over the hardware acceleration engine, wherein there are at least two CPUs which comprise a plurality of internal memory ports, the internal memory ports are coupled to the first-level internal memory unit through the internal bus, and the at least two CPUs further implements a handshake protocol through a halt signal to process a situation that the internal memory ports access the same first-level internal memory unit.