US 11,448,929 B2Granted

Array substrate with light shielding metal portions and manufacturing method thereof, display device

AssigneesOrdos Yuansheng Optoelectronics Co., Ltd., Beijing BOE Technology Development Co., Ltd.

InventorsLei Yao, Dawei Shi, Wentao Wang, Lu Yang, Haifeng Xu, Lei Yan, Jinfeng Wang, Jinjin Xue, Fang Yan, Xiaowen Si, Lin Hou, Zhixuan Guo, Yuanbo Li, Xiaofang Li

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Abstract

An array substrate and a manufacturing method thereof, and a display device are provided. The array substrate includes: a base substrate; a plurality of gate lines on a side of the base substrate; a plurality of data lines on a side of the plurality of gate lines away from the base substrate and intersecting with the plurality of gate lines; and a plurality of light shielding metal portions between the base substrate and each of the plurality of gate lines; respective one of the gate lines includes a plurality of gate line sub-segments separated by the plurality of data lines, respectively, every two adjacent gate line sub-segments in the respective one of the gate lines correspond to one of the light shielding metal portions, and the every two adjacent gate line sub-segments are connected in series through the one of the light shielding metal portions.

Claims16

Dependent claims

An array substrate, comprising:

a base substrate;
a plurality of gate lines, disposed on a side of the base substrate;
a plurality of data lines, disposed on a side of the plurality of gate lines away from the base substrate and intersecting with the plurality of gate lines;
a plurality of light shielding metal portions, disposed between the base substrate and each of the plurality of gate lines, respectively,
wherein a respective one of the gate lines comprises a plurality of gate line sub-segments separated by the plurality of data lines, respectively, every two adjacent gate line sub-segments in the respective one of the gate lines are spaced apart from each other and correspond to one of the light shielding metal portions, and the every two adjacent gate line sub-segments in the respective one of the gate lines are connected in series through the one of the light shielding metal portions;
a plurality of gate line floating segments, disposed between the base substrate and each of the data lines;
a plurality of pixel units arranged in an array, wherein a respective one of the pixel units comprises a thin film transistor, and the thin film transistor is disposed on the base substrate;
wherein a respective gate line floating segment is disposed between the every two adjacent gate line sub-segments in the respective one of the gate lines, and is insulated from corresponding two gate line sub-segments in a same layer as the respective gate line floating segment;
the thin film transistor further comprises an active layer between a respective gate line and a respective light shielding metal portion, and insulated from the respective gate line and the respective light shielding metal portion, respectively;
and
the active layer is U-shaped, and one branch of the active layer that is U-shaped intersects with the respective gate line floating segment.

8 more elements

A manufacturing method of an array substrate, comprising:

providing a base substrate, and forming a plurality of light shielding metal portions on a side of the base substrate;
forming a plurality of gate lines on a side of the plurality of light shielding metal portions away from the base substrate, wherein a respective one of the gate lines comprises a plurality of gate line sub-segments, every two adjacent gate line sub-segments in the respective one of the gate lines correspond to one of the light shielding metal portions, and the every two adjacent gate line sub-segments in the respective one of the gate lines are spaced apart from each other and are connected in series through the one of the light shielding metal portions;
forming a plurality of data lines on a side of the plurality of gate lines away from the plurality of light shielding metal portions, wherein the every two adjacent gate line sub-segments are located at two sides of a respective data line, respectively;
forming a plurality of gate line floating segments between the base substrate and each of the data lines;
forming a plurality of pixel units arranged in an array, wherein a respective one of the pixel units comprises a thin film transistor, and the thin film transistor is disposed on the base substrate;
wherein a respective gate line floating segment is between the every two adjacent gate line sub-segments in the respective one of the gate lines, and is insulated from corresponding two gate line sub-segments in a same layer as the respective gate line floating segment;
the thin film transistor further comprises an active layer between a respective gate line and a respective light shielding metal portion, and insulated from the respective gate line and the respective light shielding metal portion, respectively;
and
the active layer is U-shaped, and one branch of the active layer that is U-shaped intersects with the respective gate line floating segment.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/606,895Filed 16 May 2019
Priority: CN 201810652245.022 Jun 2018
Published: US 2021/0333608 A128 Oct 2021
Granted: 20 Sep 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

G02F 1/13606
Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit: having…
G02F 1/136209
Active matrix addressed cells: light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally…
G02F 1/136218
Active matrix addressed cells: shield electrodes
G02F 1/136286
Active matrix addressed cells: wiring, e.g. gate line, drain line