Apparatus for device access port selection
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
Estimating the term…
Abstract
The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal terminals of the device. The selecting and accessing of device access ports can be achieved when a single device is connected to the controller, when multiple devices are placed in a daisy-chain arrangement and connected to the controller, or when multiple devices are placed in a addressable parallel arrangement and connected to the controller. Additional embodiments are also provided and described in the disclosure.
Claims24
An integrated circuit comprising:
- (a) a test mode select input, a test clock input, a test data in input, and a test data out output;
- (b) access port selector controller circuitry having inputs coupled to the test mode select input, the test data in input, and the test clock input and having controller outputs and a first output enable output;
- (c) a test access port having inputs coupled to the test mode select input, the test data in input, and the test clock input, and having a second output enable output;
- and
- (d) an output enable gating circuit having a first input coupled to the first output enable output, a second input coupled to the second output enable output, and a gating circuit output coupled to an output buffer.
An integrated circuit comprising:
- (a) a test mode select input, a test clock input, a test data in input, and a test data out output;
- (b) access port selector controller circuitry including a state machine having inputs coupled to the test mode select input and the test clock input and having controller outputs and a first output enable output;
- (c) a test access port having inputs coupled to the test mode select input, the test data in input, and the test clock input, and having a second output enable output and
- (d) an output enable gating circuit having a first input coupled to the first output enable output, a second input coupled to the second output enable output, and a gating circuit output coupled to an output buffer.
Dependencies are inferred from the claim text.