Method and device for determining junction temperature of die of semiconductor power module

Method for determining the junction temperature of at least one die of a semiconductor power module, the semiconductor power module being composed of plural dies connected in parallel and switching between conducting and non conducting states according to pattern cycles, the method comprising:

• setting the at least one die in a non-conducting state during at least a fraction of one switching cycle,
• applying a current limited voltage to the gate of the at least one die during a period of time of the cycle wherein the at least one die is not conducting, the resulting voltage excursion having a value that does not enable the at least one die to be conducting,
• measuring the voltage at the gate of the at least one die,
• calculating a gate internal resistance based on the measured voltage, and
• deriving from the gate internal resistance a temperature variation of the junction of the at least one die or the temperature of the junction of the at least one die, wherein the gate of each die is not connected through one node to the gates of the other dies and a single die is disabled during one cycle.

Device for determining the junction temperature of at least one die of a semiconductor power module, the semiconductor power module being composed of plural dies connected in parallel and switching between conducting and non conducting states according to pattern cycles, the device comprises:

• processing circuitry
• to set the at least one die in a non-conducting state during at least a fraction of one switching cycle,
• to apply a current limited voltage to the gate of the at least one die during a period of time of the cycle wherein the at least one die is not conducting, the applied current limited voltage having a voltage value that does not enable the at least one die to be conducting,
• to measure the voltage at the gate of the at least one die,
• to calculate a gate internal resistance based on the measured voltage,
• to derive from the gate internal resistance a temperature variation of the junction of the at least one die or the temperature of the junction of the at least one die,
• wherein a sampling time for each voltage measurement used for calculating the gate internal resistance is limited to a time during which the at least one die is not enabled to be conducting.