# US 11,445,617 B2 · Package structure and manufacturing method thereof

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- Number: US 11,445,617 B2
- Document ID: US11445617B2
- Status: Granted
- Kind: B2
- Application number: 16/379,816
- Filed: 2019-04-10
- Published: 2019-08-01
- Granted: 2022-09-13
- Earliest claimed: 2011-10-31
- Assignees: Unimicron Technology Corp.
- Applicants: Unimicron Technology Corp.
- Inventors: Kai-Ming Yang; Chen-Hao Lin; Cheng-Ta Ko; John Hon-Shing Lau; Yu-Hua Chen; Tzyy-Jang Tseng
- Web page: https://patentgrep.com/patent/US11445617B2

## CPC

- H05K 3/4038: {Through-connections; Vertical interconnect access [VIA] connections (H05K3/403, H05K3/42 take precedence)}
- H05K 1/11: Printed elements for providing electric connections to or between printed circuits
- H05K 1/112: {directly combined with via connections}
- H05K 1/142: {Arrangements of planar printed circuit boards in the same plane, e.g. auxiliary printed circuit insert mounted in a main printed circuit}
- H05K 1/183: associated with components mounted in and supported by recessed areas of the PCBs
- H05K 3/32: electrically connecting electric components or wires to printed circuits
- H05K 3/4682: {Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/095: {of vias therein}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/635: {Through-vias}
- H10W 70/685: comprising multiple insulating layers
- H10W 70/692: Ceramics or glasses
- H10W 70/695: Organic materials
- H10W 70/698: Semiconductor materials that are electrically insulating, e.g. undoped silicon
- H10W 90/00: Package configurations
- H05K 1/185: associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards
- H05K 2201/10674: Flip chip
- H05K 2203/1469: Circuit made after mounting or encapsulation of the components
- H10W 40/10: Arrangements for heating
- H10W 72/07337: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- Y10T 29/4913: Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T 29/49146: with encapsulating, e.g., potting, etc.
- Y10T 29/49165: by forming conductive walled aperture in base
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

A package structure is disclosed herein. The package structure includes an insulating composite layer, a sealant disposed on the insulating composite layer, a first chip embedded in the sealant and having a plurality of first conductive pads exposed through the sealant, a circuit layer module having a plurality of circuit layers and a plurality of dielectric layers having a plurality of conductive vias, a second chip embedded in the circuit layer module and has a plurality of second conductive pads electrically connected to the circuit layers through the conductive vias, and a protecting layer having a plurality of openings disposed on the circuit layer module, in which the openings expose a portion of the circuit layer module.

## Claims

### Claim 1

A package structure, comprising:
an insulating composite layer having an upper surface;
a sealant disposed on the insulating composite layer and covering an entirety of the upper surface of the insulating composite layer;
a first chip embedded in the sealant, wherein the first chip has a plurality of first conductive pads disposed on an upper surface of the first chip and exposed through the sealant, a sidewall and a bottom surface of the first chip are covered by the sealant, and each of the first conductive pads has a bottom portion below the upper surface of the first chip and at least one top portion over the upper surface of the first chip, and the top portion is in contact with the bottom portion;
a circuit layer module disposed on the sealant and the first chip, wherein the circuit layer module comprises a plurality of circuit layers and a plurality of dielectric layers, each of the dielectric layers has a plurality of conductive vias, each of the circuit layers is disposed between the adjacent dielectric layers and in contact with the conductive vias, the bottommost circuit layer is electrically connected to the first conductive pads through the conductive vias, and the conductive vias are in contact with the top portions and the bottom portions of the first conductive pads;
a second chip embedded in the circuit layer module, the second chip having a plurality of second conductive pads, the second conductive pads electrically connected to the circuit layers through the conductive vias; and
a protecting layer disposed on the circuit layer module, wherein the protecting layer has a plurality of openings exposing a portion of the circuit layer module.

### Claim 2 (depends on 1)

The package structure of claim 1, wherein the second chip is disposed between the adjacent circuit layers and the dielectric layer, and is located on the circuit layers.

### Claim 3 (depends on 1)

The package structure of claim 1, further comprising a third chip embedded in the circuit layer module and located between the adjacent dielectric layers.

### Claim 4 (depends on 1)

The package structure of claim 1, wherein the insulating composite layer comprises a composite having an inorganic insulating material and an organic material.

### Claim 5 (depends on 1)

The package structure of claim 1, further comprising a metal layer disposed on the insulating composite layer, the insulating composite layer is between the sealant and the metal layer.

### Claim 6 (depends on 1)

The package structure of claim 1, wherein the second chip has a bottom surface that is free of the second conductive pads and faces the upper surface of the first chip.

### Claim 7 (depends on 1)

The package structure of claim 1, wherein the second chip has a bottom surface entirely disposed on one of the circuit layers of the circuit layer module.

### Claim 8 (depends on 1)

The package structure of claim 1, wherein the second chip has a bottom surface that is free of the second conductive pads and faces the upper surface of the first chip, wherein the bottom surface of the second chip is entirely disposed on one of the circuit layers of the circuit layer module.

### Claim 9 (depends on 1)

The package structure of claim 1, further comprising a third chip embedded in the circuit layer module, wherein the third chip has a bottom surface entirely disposed on one of the dielectric layers of the circuit layer module.

### Claim 10 (depends on 9)

The package structure of claim 9, wherein the second chip has a bottom surface entirely disposed on one of the circuit layers of the circuit layer module.

### Claim 11

A package structure, comprising:
a sealant;
a first chip embedded in the sealant, wherein the first chip has a plurality of first conductive pads exposed through the sealant, and a sidewall and a bottom surface of the first chip are covered by the sealant;
a first circuit layer module disposed on the sealant and the first chip, wherein the first circuit layer module comprises a first circuit layer and a first dielectric layer, the first dielectric layer has a at least one first conductive via, the first circuit layer is disposed on the first dielectric layer and in contact with the first conductive via, the first circuit layer is electrically connected to the first conductive pads through the first conductive via;
a second circuit layer module disposed on the first circuit layer module, wherein the second circuit layer module comprises a second circuit layer and a second dielectric layer, the second dielectric layer has at least one second conductive via, the second circuit layer is disposed on the second dielectric layer and in contact with the second conductive via;
a second chip embedded in the second circuit layer module, the second chip having a plurality of second conductive pads on an upper surface of the second chip, the second chip having a bottom surface facing the first chip and being free from the second conductive pads, the second conductive pads electrically connected to the first circuit layer through the second conductive via on the first circuit layer;
an adhesive layer directly disposed between the entire bottom surface of the second chip and the first circuit layer of the first circuit layer module, the adhesive layer directly contacting the entire bottom surface of the second chip and the first circuit layer, wherein the adhesive layer and the second chip are disposed between the second dielectric layer and the first circuit layer; and
a protecting layer disposed on the second circuit layer module, wherein the protecting layer has a plurality of openings exposing a portion of the second circuit layer module.

### Claim 12

A package structure, comprising:
a sealant;
a first chip embedded in the sealant, wherein the first chip has a plurality of first conductive pads exposed through the sealant, and a sidewall and a bottom surface of the first chip are covered by the sealant;
a circuit layer module disposed on the sealant and the first chip, wherein the circuit layer module comprises a plurality of circuit layers and a plurality of dielectric layers, each of the dielectric layers has a plurality of conductive vias, portions of the two adjacent dielectric layers are in direct contact with each other, each of the circuit layers is disposed between the two adjacent dielectric layers and in contact with the conductive vias, the bottommost circuit layer is electrically connected to the first conductive pads through the conductive vias;
a second chip embedded in the circuit layer module, the second chip having a plurality of second conductive pads on an upper surface of the second chip, the second chip having a bottom surface facing the first chip and being free from the second conductive pads, the second conductive pads electrically connected to the bottommost circuit layer through the conductive via on the bottommost circuit layer;
an adhesive layer disposed between the entire bottom surface of the second chip and the circuit layer of the circuit layer module, wherein the adhesive layer directly contacts the entire bottom surface of the second chip and the circuit layer; and
a protecting layer disposed on the circuit layer module, wherein the protecting layer has a plurality of openings exposing a portion of the circuit layer module.

### Claim 13 (depends on 12)

The package structure of claim 12, wherein each of the circuit layers disposed between the two adjacent dielectric layers is in direct contact with the two adjacent dielectric layers.