# US 11,445,139 B2 · Analog-digital converter and image sensor including thereof

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- Number: US 11,445,139 B2
- Document ID: US11445139B2
- Status: Granted
- Kind: B2
- Application number: 16/746,213
- Filed: 2020-01-17
- Published: 2020-12-17
- Granted: 2022-09-13
- Earliest claimed: 2019-06-12
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Sung Yong Kim; Kyung-Min Kim; Hyuk Oh; Hyeok Jong Lee; Seung Hoon Jung; Woong Joo; Hee Sung Chae
- Web page: https://patentgrep.com/patent/US11445139B2

## CPC

- H03M 1/123: {Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters}
- H04N 25/709: Circuitry for control of the power supply
- H03M 1/1295: {Clamping, i.e. adjusting the DC level of the input signal to a predetermined value}
- H04N 25/78: Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
- H03M 1/56: Input signal compared with linear ramp
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION

## Abstract

An analog-digital converter includes a count code generator to receive a code generation clock signal from a clock signal generator and to output a count code according to the code generation clock signal, a latch to latch the count code, an operating circuit to generate a count value of the count code and to output a digital signal based on the count value, and a transfer controller to transfer the count code from the latch to the operating circuit. The transfer controller determines whether to transfer the count code according to a logic level of a count enable clock signal generated from the clock signal generator.

## Claims

### Claim 1

An analog-digital converter, comprising:
a count code generator to receive a code generation clock signal from a clock signal generator and to output a count code according to the code generation clock signal;
a latch to latch the count code;
an operating circuit to generate a count value of the count code and to output a digital signal based on the count value; and
a transfer controller to transfer the count code from the latch to the operating circuit, the transfer controller to determine whether to transfer the count code according to a logic level of a count enable clock signal generated from the clock signal generator,
wherein the logic level of the count enable clock signal is determined according to whether the count code is stored and maintained in the latch.

### Claim 2 (depends on 1)

The analog-digital converter as claimed in claim 1, wherein the transfer controller is connected between the latch and the operating circuit.

### Claim 3 (depends on 2)

The analog-digital converter as claimed in claim 2, wherein the transfer controller includes at least one pass transistor for controlling on and off switching operations of a switch according to the logic level of the count enable clock signal.

### Claim 4 (depends on 3)

The analog-digital converter as claimed in claim 3, wherein:
when the logic level of the count enable clock signal is logic high, the switch is turned off, and the count code is not transferred to the operating circuit, and
when the logic level of the count enable clock signal is logic low, the switch is turned on, and the count code is transferred to the operating circuit.

### Claim 5 (depends on 1)

The analog-digital converter as claimed in claim 1, wherein the transfer controller is connected to an input terminal of the latch, the transfer controller to control timing when the count code is latched to the latch.

### Claim 6 (depends on 5)

The analog-digital converter as claimed in claim 5, wherein the transfer controller receives the count enable clock signal and outputs a latch enable clock signal to control timing when the count code is latched to the latch according to the logic level of the count enable clock signal.

### Claim 7 (depends on 6)

The analog-digital converter as claimed in claim 6, wherein the transfer controller outputs a first signal and a second signal having logic levels complementary to each other as the latch enable clock signal.

### Claim 8 (depends on 7)

The analog-digital converter as claimed in claim 7, wherein the latch includes:
a first tri-state inverter having an enable terminal configured to receive the first signal, and an inverse enable terminal configured to receive the second signal, an input terminal to receive the count code, and an output terminal connected to a first node;
a second tri-state inverter having an input terminal connected to the first node and an output terminal connected to a second node; and
a third tri-state inverter having an input terminal connected to the second node, and an output terminal connected to the first node.

### Claim 9 (depends on 8)

The analog-digital converter as claimed in claim 8, wherein:
a third signal complementary to the first signal is input to an enable terminal of the third tri-state inverter, and
a fourth signal complementary to the second signal is input to an inverse enable terminal of the third tri-state inverter.

### Claim 10 (depends on 9)

The analog-digital converter as claimed in claim 9, wherein phases of the third and fourth signals are advanced relative to phases of the first and second signals, respectively.

### Claim 11 (depends on 5)

The analog-digital converter as claimed in claim 5, wherein:
the transfer controller receives a comparison result signal generated by comparing a level of an input signal with a level of a reference signal and the count enable clock signal, and
the transfer controller outputs a latch enable clock signal to control timing when the count code is latched to the latch based on a logic level of the count enable clock signal and a logic level of the comparison result signal.

### Claim 12 (depends on 11)

The analog-digital converter as claimed in claim 11, wherein the latch enable clock signal has the same logic level as the logic level of the comparison result signal.

### Claim 13 (depends on 11)

The analog-digital converter as claimed in claim 11, wherein:
when the logic level of the comparison result signal is logic high, the count code is latched to the latch, and
when the logic level of the comparison result signal is logic low, the count code is not latched to the latch.

### Claim 14

An analog-digital converter, comprising:
a comparator to receive a first pixel signal during a first sensing cycle and to receive a second pixel signal during a second sensing cycle; and
a counter to output a digital signal of the second pixel signal according to a count enable clock signal,
wherein in the first and second sensing cycles, the counter does not output the digital signal when the count enable clock signal is a first level, and the counter outputs the digital signal when the count enable clock signal is a second level different from the first level, and
wherein the first level is a logic level for when a count code is not stored and maintained in a latch, and
wherein the second level is a logic level for when the count code is stored and maintained in the latch.

### Claim 15 (depends on 14)

The analog-digital converter as claimed in claim 14, wherein:
the comparator compares a level of a reference signal with levels of the first and second pixel signals and outputs a first comparison result signal and a second comparison result signal, and
the counter outputs the digital signal based on first and second count values at falling edges of the first and second comparison result signals.

### Claim 16 (depends on 15)

The analog-digital converter as claimed in claim 15, wherein:
the comparator outputs the first comparison result signal having a logic high level in a first period from a first time point when the reference signal is input to a second time point when the level of the first pixel signal is equal to the level of the reference signal,
the comparator outputs the second comparison result signal having a logic high level in a second period from a third time point when the reference signal is input to a fourth time point when the level of the second pixel signal is equal to the level of the reference signal, and
the counter generates the first and second count values in the first and second periods.

### Claim 17 (depends on 14)

The analog-digital converter as claimed in claim 14, wherein:
a count code generator configured to output a first count code and a second count code of bits different from each other, and the counter includes:
first and second latches to latch the first and second count codes, respectively;
an operating circuit connected to terminals of the first and second latches and to output the digital signal based on the first and second count codes; and
a transfer controller to transfer the first and second count codes to the operating circuit through the first and second latches, respectively, the transfer controller to determine whether to transfer the first and second count codes according to a logic level of the count enable clock signal.

### Claim 18

An image sensor comprising:
a pixel array including a plurality of pixels;
a reference signal generator to output a reference signal; and
an analog-digital converter to receive a pixel signal output from each pixel connected to column lines and the reference signal,
wherein the analog-digital converter includes:
a comparator to compare the pixel signal with the reference signal and to output a comparison result signal,
a count code generator to receive a code generation clock signal from a clock signal generator and to output a count code according to the code generation clock signal,
a latch to latch the count code,
an operating circuit connected to a terminal of the latch, to generate a count value of the count code, and to output a digital signal of the pixel signal based on the count value, and
a transfer controller to transfer the count code to the operating circuit through the latch, the transfer controller to determine whether to transfer the count code according to a logic level of a count enable clock signal generated from the clock signal generator,
wherein the logic level of the count enable clock signal is determined according to whether the count code is stored and maintained in the latch.

### Claim 19 (depends on 18)

The image sensor as claimed in claim 18, wherein:
the count code generator outputs N-bit count codes, and
the latch includes N latch circuits to latch each of the N-bit count codes.

### Claim 20 (depends on 19)

The image sensor as claimed in claim 19, wherein:
the transfer controller is connected to input terminals of each of the N latch circuits and outputs a latch enable clock signal for activating the N latches based on the count enable clock signal and the comparison result signal, and
the N latches latch each of the N-bit count codes at the same timing according to the latch enable clock signal.