# US 11,445,104 B2 · Device with a recessed gate electrode that has high thickness uniformity

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- Number: US 11,445,104 B2
- Document ID: US11445104B2
- Status: Granted
- Kind: B2
- Application number: 16/822,424
- Filed: 2020-03-18
- Published: 2020-07-09
- Granted: 2022-09-13
- Earliest claimed: 2020-03-18
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Hung-Shu Huang; Ming Chyi Liu; Tung-He Chou
- Web page: https://patentgrep.com/patent/US11445104B2

## CPC

- G03B 13/36: Autofocus systems
- G01S 3/00: Direction-finders for determining the direction from which infrasonic, sonic, ultrasonic or electromagnetic waves, or particle emission, not having a directional significance, are being received (position-fixing by co-ordinating a plurality of determinations of direction or position lines G01S5/00)
- G06V 10/40: Extraction of image or video features
- G06V 10/751: {Comparing pixel values or logical combinations thereof, or feature values having positional relevance, e.g. template matching}
- G06V 40/20: Movements or behaviour, e.g. gesture recognition (recognition of facial expressions G06V40/16)
- H04N 5/2628: {Alteration of picture size, shape, position or orientation, e.g. zooming, rotation, rolling, perspective, translation}
- H04N 23/45: for generating image signals from two or more image sensors being of different type or operating in different modes, e.g. with a CMOS sensor for moving images in combination with a charge-coupled device [CCD] for still images
- H04N 23/61: based on recognised objects
- H04N 23/63: by using electronic viewfinders
- H04N 23/675: {comprising setting of focusing regions}
- H04N 23/69: Control of means for changing angle of the field of view, e.g. optical zoom objectives or electronic zooming
- H04N 23/698: for achieving an enlarged field of view, e.g. panoramic image capture
- H04N 23/90: Arrangement of cameras or camera modules, e.g. multiple cameras in TV studios or sports stadiums
- H10D 30/0275: {forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/605: {having significant overlap between the lightly-doped extensions and the gate electrode}
- H10D 30/608: {having non-planar bodies, e.g. having recessed gate electrodes}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 64/025: {forming recessed gates, e.g. by using local oxidation}
- H10D 64/027: {by etching at gate locations}
- H10D 64/517: {characterised by the conducting layers}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 84/0142: {the gate conductors having different shapes or dimensions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- G03B: APPARATUS OR ARRANGEMENTS FOR TAKING PHOTOGRAPHS OR FOR PROJECTING OR VIEWING THEM; APPARATUS OR ARRANGEMENTS EMPLOYING ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ACCESSORIES THEREFOR (optical parts of such apparatus G02B; photosensitive materials or processes for photographic purposes G03C; apparatus for processing exposed photographic materials G03D)
- G01S: RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G06V: IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Various embodiments of the present disclosure provide a method for forming a recessed gate electrode that has high thickness uniformity. A gate dielectric layer is deposited lining a recess, and a multilayer film is deposited lining the recess over the gate dielectric layer. The multilayer film comprises a gate electrode layer, a first sacrificial layer over the gate dielectric layer, and a second sacrificial layer over the first sacrificial dielectric layer. A planarization is performed into the second sacrificial layer and stops on the first sacrificial layer. A first etch is performed into the first and second sacrificial layers to remove the first sacrificial layer at sides of the recess. A second etch is performed into the gate electrode layer using the first sacrificial layer as a mask to form the recessed gate electrode. A third etch is performed to remove the first sacrificial layer after the second etch.

## Claims

### Claim 1

A method for forming a semiconductor device, the method comprising:
forming a recess overlying a substrate;
depositing a gate dielectric layer lining and partially filling the recess;
depositing a multilayer film filling a remainder of the recess over the gate dielectric layer and comprising a gate electrode layer, a first sacrificial layer over the gate electrode layer, and a second sacrificial layer over the first sacrificial layer;
performing a planarization into the second sacrificial layer that stops on the first sacrificial layer and removes the second sacrificial layer at sides of the recess;
performing a first etch into the first and second sacrificial layers to remove the first sacrificial layer at the sides of the recess; and
performing a second etch into the gate electrode layer using the first sacrificial layer as a mask to remove the gate electrode layer at the sides of the recess and to form a gate electrode underlying the first sacrificial layer in the recess.

### Claim 2 (depends on 1)

The method according to claim 1, further comprising:
performing a third etch into the first sacrificial layer after the second etch to remove the first sacrificial layer from atop the gate electrode; and
performing a fourth etch to remove the gate dielectric layer at the sides of the recess.

### Claim 3 (depends on 2)

The method according to claim 2, wherein the third and fourth etches are performed by a common wet etching process using the same etchant.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the first and second etches are performed by a common dry etching process.

### Claim 5 (depends on 1)

The method according to claim 1, wherein the first etch is a non-selective etch having substantially the same etch rates for the first and second sacrificial layers, and wherein the second etch is a selective etch having a high etch rate for the gate electrode layer relative to the first sacrificial layer.

### Claim 6 (depends on 1)

The method according to claim 1, wherein the forming of the recess comprises performing an etch into the substrate to form the recess in the substrate.

### Claim 7 (depends on 1)

The method according to claim 1, further comprising:
forming a hard mask covering the gate electrode;
forming a pair of source/drain regions in the substrate, respectively on opposite sides of the gate electrode, while the hard mask covers the gate electrode; and
patterning the hard mask to form an opening exposing the gate electrode, wherein the hard mask partially covers the gate electrode after the patterning.

### Claim 8

A method for forming a semiconductor device, the method comprising:
forming a recess overlying a substrate;
depositing a gate dielectric layer lining and partially filling the recess;
depositing a gate electrode layer covering the substrate and lining the recess over the gate dielectric layer, wherein the gate electrode layer has a recessed surface recessed into a top of the gate electrode layer at the recess;
forming a mask covering the recessed surface and recessed into the top of the gate electrode layer, wherein a width of the mask is less than a width of the recess; and
performing an etch into the gate electrode layer with the mask in place to form a gate electrode in the recess.

### Claim 9 (depends on 8)

The method according to claim 8, wherein the forming of the recess comprises performing a second etch into a top of the substrate, such that the recess extends into the top of the substrate.

### Claim 10 (depends on 8)

The method according to claim 8, wherein the forming of the recess comprises:
forming an interlayer dielectric (ILD) layer over the substrate;
forming a dummy structure embedded in the ILD layer and having a top surface level with a top surface of the ILD layer; and
removing the dummy structure, such that the recess replaces the dummy structure.

### Claim 11 (depends on 8)

The method according to claim 8, wherein the mask has a pair of protrusions respectively on opposite sides of the mask and extending along and directly contacting individual sidewalls of the gate electrode layer.

### Claim 12 (depends on 8)

The method according to claim 8, wherein the recessed surface is elevated relative to a top surface of the gate dielectric layer, and wherein the etch forms the gate electrode with a pair of depressions respectively on opposite sides of the gate electrode where uncovered by the mask.

### Claim 13 (depends on 8)

The method according to claim 8, wherein the recessed surface is recessed relative to a top surface of the gate dielectric layer, and wherein the etch forms the gate electrode with a pair of upward protrusions respectively on opposite sides of the gate electrode where uncovered by the mask.

### Claim 14 (depends on 8)

The method according to claim 8, wherein the forming of the mask comprises:
depositing a first sacrificial layer covering the gate electrode layer;
depositing a second sacrificial layer covering the first sacrificial layer and recessed into a top of the first sacrificial layer;
performing a planarization into the second sacrificial layer until the top of the first sacrificial layer is reached; and
performing a second etch into the first and second sacrificial layers until the gate electrode layer is reached.

### Claim 15

A method for forming a semiconductor device, the method comprising:
depositing a gate dielectric layer overlying a substrate;
forming a gate electrode layer covering the gate dielectric layer and recessed into a top of the gate dielectric layer, wherein a top of the gate electrode layer has a recess;
depositing a sacrificial layer covering the gate electrode layer, and further lining the recess over the gate electrode layer;
forming a mask filling the recess over the sacrificial layer; and
performing a series of one or more etches into the sacrificial layer and the gate electrode layer to form a gate electrode recessed into the top of the gate dielectric layer;
wherein the series of one or more etches recesses top surface portions of the gate electrode layer uncovered by the mask to level with, or recessed relative to, a top surface of the gate dielectric layer.

### Claim 16 (depends on 15)

The method according to claim 15, further comprising:
forming a trench isolation structure extending into a top of the substrate, wherein the trench isolation structure comprises a dielectric material; and
performing an additional etch into the top of the substrate and a top of the trench isolation structure to form a second recess;
wherein the gate dielectric layer is deposited lining the second recess, and wherein the recess of the gate electrode layer is directly over the second recess.

### Claim 17 (depends on 16)

The method according to claim 16, further comprising:
forming a first source/drain and a second source/drain region respectively on opposite sides of the gate electrode, wherein the trench isolation structure is between the second source/drain region and the gate electrode.

### Claim 18 (depends on 15)

The method according to claim 15, wherein the mask is formed with a concave top surface recessed relative to a top surface of the sacrificial layer.

### Claim 19 (depends on 15)

The method according to claim 15, wherein the forming of the mask comprises:
depositing a second sacrificial layer over the sacrificial layer, wherein the second sacrificial layer is recessed into a top of the sacrificial layer directly over the recess; and
performing a planarization into the second sacrificial layer until the sacrificial layer is reached.

### Claim 20 (depends on 15)

The method according to claim 15, further comprising:
forming a pair of source/drain regions on the substrate;
depositing a dielectric layer covering the substrate and the source/drain regions; and
performing an additional etch into a top of the dielectric layer to form a second recess exposing the substrate between the source/drain regions;
wherein the gate dielectric layer is deposited lining the second recess, and wherein the recess of the gate electrode layer is directly over the second recess.