# US 11,445,020 B2 · Circuitry and method

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- Number: US 11,445,020 B2
- Document ID: US11445020B2
- Status: Granted
- Kind: B2
- Application number: 16/828,207
- Filed: 2020-03-24
- Published: 2021-09-30
- Granted: 2022-09-13
- Earliest claimed: 2020-03-24
- Assignees: Arm Limited
- Applicants: Arm Limited
- Inventors: Jonathan Curtis Beard; Jamshed Jalal; Curtis Glenn Dunham; Roxana Rusitoru
- Web page: https://patentgrep.com/patent/US11445020B2

## CPC

- G06F 12/0813: with a network or matrix configuration
- H04L 67/1095: Replication or mirroring of data, e.g. scheduling or transport for data synchronisation between network nodes
- G06F 11/0784: {Routing of error reports, e.g. with a specific transmission path or data flow}
- G06F 11/1451: {by selection of backup contents}
- G06F 11/3034: {where the computing system component is a storage system, e.g. DASD based or network based (digital input from or digital output to record carriers G06F3/06; digital recording or reproducing G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097)}
- G06F 12/0808: with cache invalidating means (G06F12/0815 takes precedence)
- G06F 12/0815: Cache consistency protocols
- G06F 12/0826: {Limited pointers directories; State-only directories without pointers}
- G06F 12/0828: {with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions}
- G06F 12/084: with a shared cache
- G06F 12/0868: Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
- G06F 15/7825: {Globally asynchronous, locally synchronous, e.g. network on chip}
- G06F 12/0833: {in combination with broadcast means (e.g. for invalidation or updating)}
- G06F 2212/1024: Latency reduction
- G06F 2212/621: Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
- G06F 2212/656: Address space sharing
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

Circuitry comprises a set of data handling nodes comprising: two or more master nodes each having respective storage circuitry to hold copies of data items from a main memory, each copy of a data item being associated with indicator information to indicate a coherency state of the respective copy, the indicator information being configured to indicate at least whether that copy has been updated more recently than the data item held by the main memory; a home node to serialise data access operations and to control coherency amongst data items held by the set of data handling nodes so that data written to a memory address is consistent with data read from that memory address in response to a subsequent access request; and one or more slave nodes including the main memory; in which: a requesting node of the set of data handling nodes is configured to communicate a conditional request to a target node of the set of data handling nodes in respect of a copy of a given data item at a given memory address, the conditional request being associated with an execution condition and being a request that the copy of the given data item is written to a destination node of the data handling nodes; and the target node is configured, in response to the conditional request: (i) when the outcome of the execution condition is successful, to write the data item to the destination node and to communicate a completion-success indicator to the requesting node; and (ii) when the outcome of the execution condition is a failure, to communicate a completion-failure indicator to the requesting node.

## Claims

### Claim 1

Circuitry having:
a set of data handling nodes comprising:
two or more master nodes each having respective storage circuitry to hold copies of data items from a main memory, each copy of a data item being associated with indicator information to indicate a coherency state of the respective copy, the indicator information being configured to indicate at least whether that copy has been updated more recently than the data item held by the main memory;
a home node to serialise data access operations and to control coherency amongst data items held by the set of data handling nodes so that data written to a memory address is consistent with data read from that memory address in response to a subsequent access request; and
one or more slave nodes including the main memory;
in which:
a requesting node of the set of data handling nodes is configured to communicate a conditional request to a target node of the set of data handling nodes in respect of a copy of a given data item at a given memory address, the conditional request being associated with an execution condition comprising a logical comparison of a plurality of conditions with respective target outcomes, the conditional request being a request that the copy of the given data item is written to a destination node of the data handling nodes; and
the target node is configured, in response to the conditional request:
(i) when the outcome of the execution condition is successful, to write the data item to the destination node and to communicate a completion-success indicator to the requesting node; and
(ii) when the outcome of the execution condition is a failure, to communicate a completion-failure indicator to the requesting node.

### Claim 2 (depends on 1)

The circuitry of claim 1, in which the indicator information is configured to indicate whether the respective copy is a unique copy amongst the set of data handling nodes.

### Claim 3 (depends on 2)

The circuitry of claim 2, in which the requesting node is configured to communicate the conditional request in respect of the copy of the given data item when the indicator information associated with that copy indicates that the respective copy is a unique copy amongst the set of data handling nodes.

### Claim 4 (depends on 1)

The circuitry of claim 1, in which the target node is the home node.

### Claim 5 (depends on 1)

The circuitry of claim 1, in which the logical comparison is a comparison which requires all of the plurality of conditions to have their respective target outcomes.

### Claim 6 (depends on 5)

The circuitry of claim 5, in which the destination node is the main memory.

### Claim 7 (depends on 6)

The circuitry of claim 6, in which:
the step (i) comprises controlling the indicator information associated with the copy of the given data item to indicate that the copy of the given data item has not been updated more recently than the data item held by the main memory; and
the step (ii) comprises controlling the indicator information associated with the copy of the given data item to indicate that the copy of the given data item has been updated more recently than the data item held by the main memory.

### Claim 8 (depends on 7)

The circuitry of claim 7, in which the requesting node is configured, in response to receipt of the completion-success indicator, to set the indicator information associated with the copy of the given data item to indicate that the main memory holds the most up to date version of the given data item.

### Claim 9 (depends on 6)

The circuitry of claim 6, in which, in the case that at communication of the conditional request to the target node, the indicator information associated with the copy of the given data item indicates that the main memory holds the most up to date version of the given data item, the target node is configured not to control any change to the indicator information.

### Claim 10 (depends on 1)

The circuitry of claim 1, in which each data handling node is configured to hold the indicator data associated with a copy of a data item held by that data handling node.

### Claim 11 (depends on 10)

The circuitry of claim 10, in which the destination node is a master node or the home node.

### Claim 12 (depends on 11)

The circuitry of claim 11, in which:
the step (i) comprises controlling the indicator information associated with the copy of the given data item to indicate that the copy of the given data item at the requesting node is invalid; and
the step (ii) comprises controlling the indicator information associated with the copy of the given data item to indicate that the copy of the given data item has been updated more recently than the data item held by the main memory.

### Claim 13 (depends on 12)

The circuitry of claim 12, in which the requesting node is configured, in response to receipt of the completion-failure indicator, to set the indicator information associated with the copy of the given data item to indicate that the copy of the given data item has been updated more recently than the data item held by the main memory.

### Claim 14 (depends on 11)

The circuitry of claim 11, in which the execution condition represents whether the destination node is currently able to receive the data item.

### Claim 15 (depends on 1)

The circuitry of claim 1, in which the execution condition represents whether the target node is currently able to control writing of the data item to the destination node.

### Claim 16 (depends on 1)

The circuitry of claim 1, in which the requesting node of the set of data handling nodes is configured to initiate a sequence of operations requiring exclusive access to data at a given memory address, the sequence of operations including an exclusive store operation to the given memory address.

### Claim 17 (depends on 16)

The circuitry of claim 16, in which the requesting node is configured to implement the exclusive store operation using the conditional request.

### Claim 18 (depends on 17)

The circuitry of claim 17, in which the exclusive store operation comprises setting a particular value to data representing an exclusivity monitor.

### Claim 19

A method comprising:
communicating data between a set of data handling nodes comprising:
two or more master nodes each having respective storage circuitry to hold copies of data items from a main memory, each copy of a data item being associated with indicator information to indicate a coherency state of the respective copy, the indicator information being configured to indicate at least whether that copy has been updated more recently than the data item held by the main memory;
a home node to serialise data access operations and to control coherency amongst data items held by the set of data handling nodes so that data written to a memory address is consistent with data read from that memory address in response to a subsequent access request; and
one or more slave nodes including the main memory;
a requesting node of the set of data handling nodes communicating a conditional request to a target node of the set of data handling nodes in respect of a copy of a given data item at a given memory address, the conditional request being associated with an execution condition comprising a logical comparison of a plurality of conditions with respective target outcomes, the conditional request being a request that the copy of the given data item is written to a destination node of the data handling nodes; and
the target node, in response to the conditional request:
(i) writing, when the outcome of the execution condition is successful, the data item to the destination node and to communicate a completion-success indicator to the requesting node; and
(ii) communicating, when the outcome of the execution condition is a failure, a completion-failure indicator to the requesting node.