# US 11,444,748 B2 · Ultra-low latency advanced encryption standard

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,444,748 B2
- Document ID: US11444748B2
- Status: Granted
- Kind: B2
- Application number: 16/369,103
- Filed: 2019-03-29
- Published: 2019-07-25
- Granted: 2022-09-13
- Earliest claimed: 2019-03-29
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Michael Kounavis
- Web page: https://patentgrep.com/patent/US11444748B2

## CPC

- H04L 9/0631: {Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms}
- H04L 9/3026: {details relating to polynomials generation, e.g. generation of irreducible polynomials}
- H04L 2209/122: Hardware reduction or efficient architectures
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

In one example, an apparatus for Advanced Encryption Standard (AES) substitutions box (S-box) encryption includes an S-Box logic function and a MixColumns multiplication operation. The S-box logic function takes as input a state and is an 8-bit to 8-bit logic function, and wherein the S-box logic function is minimized such that an S-box round comprises nine not-and (NAND) levels and duplications of a logical product of the minimized S-box logic function are eliminated. The MixColumns multiplication operation comprises a plurality of factors that are exclusive ORed (XOR) with an output of the S-box round to obtain a scaled 16-byte output.

## Claims

### Claim 1

A method to enable an Advanced Encryption Standard (AES) substitution box (S-box), comprising:
finding, via AES circuitry, prime implicants of an S-box logic function;
determining, via the AES circuitry, essential implicants from the prime implicants of the S-box function;
minimizing, via the AES circuitry, the essential implicants and finding selected implicants;
removing, via the AES circuitry, duplications from the essential implicants and the selected implicants to obtain final implicants;
expressing, via the AES circuitry, the S-box logic function as the final implicants; and
scaling, via the AES circuitry, the S-box logic function expressed as final implicants by factors from a MixColumns multiplication operation, wherein the S-box logic function and the MixColumns multiplication operation comprise nine NAND levels and five XOR levels.

### Claim 2 (depends on 1)

The method of claim 1, wherein the MixColumns multiplication operation is combined with the S-box logic function, and the combined the S-box logic function is minimized such that an AES round comprises nine NAND levels and three XOR levels, and duplications of a logical product of the minimized S-box logic function are eliminated.

### Claim 3 (depends on 1)

The method of claim 1, wherein columns of an output of the scaled S-box logic function are XORed to derive an 8-bit output.

### Claim 4 (depends on 1)

The method of claim 1, wherein minimizing the essential implicants and finding selected implicants comprises:
expressing the S-box function as a set of implicants;
searching the set of implicants for essential implicants and selected implicants; and;
expressing the S-box function as the essential implicants and the selected implicants.

### Claim 5 (depends on 1)

The method of claim 1, wherein the MixColumns multiplication operation is combined with the S-box logic function, and minimizing the combined the S-box logic function comprises:
expressing the combined S-box function as a set of implicants;
searching the set of implicants for essential implicants and selected implicants; and;
expressing the combined S-box function as the essential implicants and the selected implicants.

### Claim 6 (depends on 1)

The method of claim 1, wherein duplications of a logical product of the minimized S-box logic function are removed by iteratively searching a plurality of regions for substitute logical products.

### Claim 7 (depends on 1)

The method of claim 1, wherein the plurality of factors is obtained from a fixed polynomial such that columns of the state are evaluated as polynomials over GF(28) and multiplied modulo X4+1 with the fixed polynomial.

### Claim 8 (depends on 1)

The method of claim 1, wherein the S-box logic function encrypts data at a processing core and transmits the encrypted data to an L1 cache.

### Claim 9 (depends on 1)

The method of claim 1, wherein the S-box logic function is to encrypt data stored in a register of a computing device.