# US 11,444,746 B1 · Phasing detection of asynchronous dividers > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,444,746 B1 - Document ID: US11444746B1 - Status: Granted - Kind: B1 - Application number: 17/303,757 - Filed: 2021-06-07 - Granted: 2022-09-13 - Earliest claimed: 2021-06-07 - Assignees: Analog Devices, Inc. - Applicants: Analog Devices, Inc. - Inventors: John Kenney; Robert Schell - Web page: https://patentgrep.com/patent/US11444746B1 ## CPC - H04L 7/0008: {Synchronisation information channels, e.g. clock distribution lines} - H03K 21/08: Output circuits - H03L 7/0807: {concerning mainly a recovery circuit for the reference signal} - H03L 7/095: using a lock detector (H03L7/087 takes precedence) - H03L 7/0995: {the oscillator comprising a ring oscillator} - H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) ## Abstract Apparatus and methods for phasing detection of asynchronous dividers are provided herein. In certain embodiments, a clock and data recovery system includes a first divider that outputs a first divided clock signal, a second divider that outputs a second divided clock signal, and an asynchronous clock phasing detection circuit that generates a detection signal indicating a relative phase difference between the first divided clock signal and the second divided clock signal. The asynchronous clock phasing detection circuit includes a quantization and logic circuit that generates an output signal indicating when the first divided clock signal and the second divided clock signal are in different states, an oscillator that outputs a control clock signal, a first counter controlled by the control clock signal and configured to count the output signal, and a control circuit that processes a first count signal from the first counter to generate the detection signal. ## Claims ### Claim 1 A clock and data recovery (CDR) system comprising: a first divider configured to output a first divided clock signal; a second divider configured to output a second divided clock signal; and an asynchronous clock phasing detection circuit comprising: a comparison circuit configured to process the first divided clock signal and the second divided clock signal to generate an output signal indicating when the first divided clock signal and the second divided clock signal are in different states; an oscillator configured to output a control clock signal; a first counter controlled by the control clock signal and configured to count the output signal; and a control circuit configured to process a first count signal from the first counter to generate a detection signal indicating a relative phasing between the first divided clock signal and the second divided clock signal, wherein the detection signal is operable to control a state of at least one of the first divider or the second divider. ### Claim 2 (depends on 1) The CDR system of claim 1, further comprising a second counter configured to count a number of cycles of the control clock signal, the control circuit further configured to generate the detection signal based on ratio of the first count signal from the first counter and a second count signal from the second counter. ### Claim 3 A clock and data recovery (CDR) system comprising: a first divider configured to output a first divided clock signal; a second divider configured to output a second divided clock signal; and an asynchronous clock phasing detection circuit comprising: a comparison circuit configured to process the first divided clock signal and the second divided clock signal to generate an output signal indicating when the first divided clock signal and the second divided clock signal are in different states; an oscillator configured to output a control clock signal; a first counter controlled by the control clock signal and configured to count the output signal; and a control circuit configured to process a first count signal from the first counter to generate a detection signal indicating a relative phasing between the first divided clock signal and the second divided clock signal, wherein the control circuit is configured to control the oscillator to set an oscillation frequency of the control clock signal. ### Claim 4 (depends on 3) The CDR system of claim 3, wherein the first divided clock signal and the second divided clock signal have a clock period, the control circuit configured to control the oscillator to perform a random walk across the clock period. ### Claim 5 (depends on 1) The CDR system of claim 1, wherein the comparison circuit includes a first quantizer configured to generate a first quantized clock signal based on quantizing the first clock signal, a second quantizer configured to generate a second quantized clock signal based on quantizing the second clock signal, and a logic gate configured to generate the output signal based on the first quantized clock signal and the second quantized clock signal. ### Claim 6 (depends on 5) The CDR system of claim 5, wherein the first quantizer and the second quantizer are configured to receive the control clock signal from a pair of balanced clock signal routes. ### Claim 7 (depends on 5) The CDR system of claim 5, wherein the logic gate is an exclusive or gate. ### Claim 8 (depends on 1) The CDR system of claim 1, wherein the comparison circuit includes a logic gate configured to generate a logic signal based on the first clock signal and the second clock signal, and a quantizer configured to generate the output signal based on quantizing the logic signal. ### Claim 9 (depends on 1) The CDR system of claim 1, wherein the oscillator is a ring oscillator. ### Claim 10 A method of asynchronous clock phasing detection, the method comprising: dividing a first clock signal to generate a first divided clock signal using a first divider; dividing a second clock signal to generate a second divided clock signal using a second divider; generating an output signal indicating when the first divided clock signal and the second divided clock signal are in different states; generating a first count signal by counting the output signal based on timing of a control clock signal using a first counter; generating a detection signal indicating a relative phasing between the first divided clock signal and the second divided clock signal based on the first count signal; generating a second count signal by counting a number of cycles of the control clock signal, and generating the detection signal based on ratio of the first count signal and the second count signal. ### Claim 11 (depends on 10) The method of claim 10, wherein the first divided clock signal and the second divided clock signal have a clock period, the method further comprising varying a frequency of the control clock signal to perform a random walk across the clock period. ### Claim 12 A method of asynchronous clock phasing detection, the method comprising: dividing a first clock signal to generate a first divided clock signal using a first divider; dividing a second clock signal to generate a second divided clock signal using a second divider; genera tin output signal indicating when the first divided clock signal and the second divided clock signal are in different states; generating a first count signal by counting the output signal based on timing of a control clock signal using a first counter; generating a detection signal indicating a relative phasing between the first divided clock signal and the second divided clock signal based on the first count signal; and controlling a state of at least one of the first divider or the second divider based on the detection signal. ### Claim 13 An asynchronous clock phasing detection circuit comprising: a comparison circuit configured to process a first divided clock signal and a second divided clock signal to generate an output signal indicating when the first divided clock signal and the second divided clock signal are in different states; an oscillator configured to output a control clock signal; a first counter controlled by the control clock signal and configured to count the output signal; a control circuit configured to process a first count signal from the first counter to generate a detection signal indicating a relative phasing between the first divided clock signal and the second divided clock signal; and a second counter configured to count a number of cycles of the control clock signal, the control circuit further configured to generate the detection signal based on ratio of the first count signal from the first counter and a second count signal from the second counter. ### Claim 14 (depends on 13) The asynchronous clock phasing detection circuit of claim 13, wherein the first divided clock signal and the second divided clock signal have a clock period, the control circuit configured to control the oscillator to perform a random walk across the clock period. ### Claim 15 (depends on 13) The asynchronous clock phasing detection circuit of claim 13, wherein the comparison circuit is configured to quantize the first divided clock signal to generate a first quantized clock signal, to quantize the second divided clock signal to generate a second quantized clock signal, and to generate the output signal based on a logical operation of the first quantized clock signal and the second quantized clock signal. ### Claim 16 (depends on 13) The asynchronous clock phasing detection circuit of claim 13, wherein the comparison circuit is configured to generate a logic signal based on a logical operation of the first divided clock signal and the second divided clock signal, and to generate the output signal based on quantizing the logic signal. ### Claim 17 (depends on 13) The asynchronous clock phasing detection circuit of claim 13, wherein the oscillator is a ring oscillator. ### Claim 18 (depends on 10) The method of claim 10, further comprising controlling the oscillator to set an oscillation frequency of the control clock signal. ### Claim 19 (depends on 12) The method of claim 12, further comprising controlling the oscillator to set an oscillation frequency of the control clock signal. ### Claim 20 (depends on 12) The method of claim 12, wherein the first divided clock signal and the second divided clock signal have a clock period, the method further comprising varying a frequency of the control clock signal to perform a random walk across the clock period.