# US 11,444,633 B2 · Near zero power fully integrated digital conversion, sensors and sensing methods > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,444,633 B2 - Document ID: US11444633B2 - Status: Granted - Kind: B2 - Application number: 17/285,289 - Filed: 2019-10-14 - Published: 2021-08-05 - Granted: 2022-09-13 - Earliest claimed: 2018-10-15 - Assignees: The Regents of the University of California - Applicants: The Regents of the University of California - Inventors: Hui Wang; Patrick Mercier - Web page: https://patentgrep.com/patent/US11444633B2 ## CPC - H03M 1/38: sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) - G01K 7/00: Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat (giving results other than momentary value of temperature G01K3/00) {; Power supply therefor, e.g. using thermoelectric elements} - H03M 1/56: Input signal compared with linear ramp - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - G01K: MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR (radiation pyrometry G01J5/00) ## Abstract A charging to digital converter sensor in a CMOS integrated circuit digitizes a sensed property by comparing charging time between two paths and adjusting the charging rate of one of the two paths by increasing or decreasing the amount of capacitance in that path, until both of the two paths have the same charging time to reach respective constant with sensed property and proportional with sensed property reference voltages or currents. Sub nanowatt operation is achieved with preferred circuits. A method directly digitizes, on-chip, a charging time comparison of two ramp voltages that are compared to respective constant with sensed property and proportional with sensed property reference voltages or currents. ## Claims ### Claim 1 A charging to digital converter sensor in a CMOS integrated circuit, the sensor comprising: a voltage or current reference generator that generates a first reference voltage or current that is constant with respect to a sensed property; a voltage or current reference generator that generates a second reference voltage or current that varies with respect to the sensed property; two paths including on-chip capacitors charged with a sub nanowatt current reference such that a first ramp voltage or current is generated in one of the two paths and a second ramp voltage or current is generated in a second of the two paths, wherein the first ramp voltage or current is compared to the first reference voltage or current and the second ramp voltage or current is compared to the second reference voltage or current; a digitizer for digitizing the sensed property by comparing charging time between the two paths and adjusting the charging rate of one of the two paths by increasing or decreasing the amount of capacitance in that path, until both of the two paths have the same charging time to reach the first and second reference voltages or currents, respectively, wherein a digital output represents a value of the capacitance; and digital feedback to reset the converter to restart the charging time. ### Claim 2 (depends on 1) The circuit of claim 1, wherein the sub nanowatt current reference is generated by biasing a gate leakage device with a three-transistor constant with sensed property voltage or current reference generator. ### Claim 3 (depends on 1) The sensor of claim 1, wherein the sub nanowatt current reference comprises a picoamp current reference that is a gate leakage transistor biased by a voltage reference generator. ### Claim 4 (depends on 3) The sensor of claim 3, wherein the voltage or current reference generators comprise voltage reference generators and consist of an OFF-state PMOS on top of a diode-connected NMOS and another NMOS in an OFF state. ### Claim 5 (depends on 4) The sensor of claim 4, wherein the sub nanowatt current reference comprises a gate-leakage transistor as a large resistor and mirrors current in the leakage transistor. ### Claim 6 (depends on 1) The sensor of claim 1, wherein the digital feedback comprises a binary search algorithm the searches successively from most significant bit (MSB) to least significant bit (LSB). ### Claim 7 (depends on 1) The sensor of claim 1, wherein the digital feedback comprises a LSB-first successive approximation register (SAR) that updates from the LSB to MSB and determines the effective MSB for each conversion, followed by an SAR conversion that dynamically adjusts the length of the SAR logic that is necessary for each conversion. ### Claim 8 (depends on 1) The sensor of claim 1, wherein the sensed property is temperature and the sub nanowatt current reference consists of a single constant with temperature current reference. ### Claim 9 A method for charging to digital converter sensing in a CMOS integrated circuit, the method comprising: generating two ramp voltages or currents by charging two on-chip capacitors with a sub nanowatt current reference generator; comparing, on-chip, a first of the two ramp voltages or currents to a constant with sensed property voltage or current and a second of the ramp voltages or currents with proportional to sensed property voltage or current; and directly digitizing, on-chip, a charging time comparison of the two ramp voltages or currents to provide a sensed value. ### Claim 10 (depends on 9) The method of claim 9, wherein the sensed value is temperature. ### Claim 11 (depends on 9) The method of claim 9, wherein the on-chip capacitors comprise metal-insulator-metal (MIM) capacitor.