Tracking analog-to-digital converter for power converters

A method of tracking a voltage via a tracking analog-to-digital converter (ADC), the method comprising:

• tracking, via a first tracking loop of the tracking ADC, a voltage input to the tracking ADC, the first tracking loop having a multi-cycle latency which increases a residual error of the voltage tracking provided by the first tracking loop;
• and
• supplementing, via a second tracking loop of the tracking ADC, the voltage tracking provided by the first tracking loop and reducing the residual error of the voltage tracking for dynamic changes at the voltage input, the second tracking loop having a single-cycle latency,
• wherein the tracking via the first tracking loop comprises:
• generating a first tracking reference adjustment each clock cycle and that corresponds to a code value;
• generating an error value each clock cycle based on the voltage input to the tracking ADC and the first tracking reference adjustment;
• and
• storing the error value generated each clock cycle,
• wherein the supplementing via the second tracking loop comprises generating a second tracking reference adjustment based on the error value generated each clock cycle.

An electronic system, comprising:

• a circuit board;
• a load attached to the circuit board;
• and
• a power converter configured to provide an output voltage to the load,
• wherein the power converter comprises:
• at least one phase configured to provide a phase current to the load;
• and
• a controller configured to control switching of the at least one phase,
• wherein the controller comprises a tracking analog-to-digital converter (ADC) configured to measure the output voltage,
• wherein the tracking ADC comprises:
• a first tracking loop configured to track the output voltage, the first tracking loop comprising a first digital-to-analog converter (DAC) configured to generate a first tracking reference adjustment that corresponds to a code value input to the first DAC each clock cycle, a comparator configured to generate an error value each clock cycle based on the output voltage and the first tracking reference adjustment, and a first latch configured to store the error value generated by the comparator each clock cycle, wherein the comparator is actuated based on an edge of a clock signal that sets the frequency of each clock cycle and the first latch is actuated a fixed time after the comparator but before the clock cycle is completed;
• and
• a second tracking loop configured to supplement the voltage tracking provided by the first tracking loop and reduce a residual error of the voltage tracking for dynamic changes in the output voltage, the second tracking loop having a single-cycle latency.