# US 11,444,627 B1 · Synchronization of receiver and transmitter local oscillators for ranging applications > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,444,627 B1 - Document ID: US11444627B1 - Status: Granted - Kind: B1 - Application number: 17/549,314 - Filed: 2021-12-13 - Granted: 2022-09-13 - Earliest claimed: 2021-12-13 - Assignees: Silicon Laboratories Inc. - Applicants: Silicon Laboratories Inc. - Inventors: Rangakrishnan Srinivasan; Michael Wu; Francesco Barale; John Khoury; Aslamali A. Rafi - Web page: https://patentgrep.com/patent/US11444627B1 ## CPC - H03L 7/099: concerning mainly the controlled oscillator of the loop - H03L 7/18: using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) - G06F 1/08: Clock generators with changeable or programmable clock frequency - H03C 3/0933: {using fractional frequency division in the feedback loop of the phase locked loop} - H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) - H03L 7/23: with pulse counters or frequency dividers - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03C: MODULATION (masers or lasers H01S; coding, decoding or code conversion H03M) ## Abstract A system and method for accurately determining a distance between two network devices using a Channel Sounding application is disclosed. The network devices each guarantee a fixed phase relationship between the transmit circuit and the receive circuit. In one embodiment, this is achieved by incorporating the divider within the phase locked loop. The divider may have a reset, such that it can be initialized to a predetermined state. Further, by utilizing a divider disposed within the phase locked loop with a reset, the quadrature signal generator is guaranteed to output clocks for the transmit circuit and the receive circuit that have a constant phase relationship. ## Claims ### Claim 1 A clock generation circuit, comprising: a signal source to provide a REFCLK signal; and a phase locked loop, comprising: a detector to determine a difference between the REFCLK signal and a feedback signal and provide an output based on the difference; a loop filter to filter the output to create a filtered output; an oscillator to generate a clock signal with a frequency related to the filtered output; a divider to divide the clock signal by a quantity; and a multi-modulus divider in communication with an output of the divider, to further divide the output of the divider and supply the feedback signal to the detector; wherein the divider comprises a reset signal so as to be initialized to a known state. ### Claim 2 (depends on 1) The clock generation circuit of claim 1, further comprising a quadrature signal generator in communication with the output of the divider. ### Claim 3 (depends on 2) The clock generation circuit of claim 2, wherein the quadrature signal generator outputs a transmit clock and a receive clock, and wherein a phase difference between the transmit clock and the receive clock is constant. ### Claim 4 (depends on 3) The clock generation circuit of claim 3, wherein the quadrature signal generator comprises a shift register. ### Claim 5 (depends on 4) The clock generation circuit of claim 4, wherein the quadrature signal generator comprises combinational logic, wherein the shift register and the combinational logic are used to generate the receive clock and the transmit clock. ### Claim 6 (depends on 5) The clock generation circuit of claim 5, wherein the receive clock output by the quadrature signal generator has a duty cycle of 12.5%, 25% or 50%. ### Claim 7 (depends on 4) The clock generation circuit of claim 4, wherein the shift register is used to generate the transmit clock. ### Claim 8 (depends on 7) The clock generation circuit of claim 7, wherein the transmit clock output by the quadrature signal generator has a duty cycle of 12.5%, 25% or 50%. ### Claim 9 (depends on 1) The clock generation circuit of claim 1, wherein the detector comprises a phase/frequency detector and charge pump; and the oscillator comprises a voltage-controlled oscillator and the output from the phase/frequency detector and charge pump and the loop filter is a voltage. ### Claim 10 (depends on 1) The clock generation circuit of claim 1, wherein the detector comprises a time to digital converter, the output from the loop filter comprises a digital word and the oscillator comprises a digital-controlled oscillator. ### Claim 11 A method of performing a distance measurement between a first network device and a second network device, comprising: transmitting a first packet from the first network device to the second network device, using a first frequency; replying to the first packet by transmitting a second packet from the second network device to the first network device using the first frequency; transmitting a third packet from the first network device to the second network device using a second frequency, different from the first frequency; replying to the third packet by transmitting a fourth packet from the second network device to the first network device using the second frequency; and calculating a distance based on a phase received by the first network device and the second network device for each packet, the first frequency and the second frequency, wherein the first network device and the second network device each comprise a clock generation circuit to generate a receive clock and a transmit clock, wherein a phase difference between the transmit clock and the receive clock of each network device is constant. ### Claim 12 (depends on 11) The method of claim 11, wherein the clock generation circuit comprises: a signal source to provide a REFCLK signal; and a phase locked loop, comprising: a detector to determine a difference between the REFCLK signal and a feedback signal and provide an output based on the difference; a loop filter to filter the output to create a filtered output; an oscillator to generate a clock signal with a frequency related to the filtered output; a divider to divide the clock signal by a quantity; and a multi-modulus divider in communication with an output of the divider, to further divide the output of the divider and supply the feedback signal to the detector, wherein the receive clock and the transmit clock of each network device is generated from the output of the divider. ### Claim 13 (depends on 12) The method of claim 12, wherein the divider comprises a reset signal so as to be initialized to a known state. ### Claim 14 (depends on 12) The method of claim 12, wherein the detector comprises a phase/frequency detector and charge pump; and the oscillator comprises a voltage-controlled oscillator and the output from the phase/frequency detector and charge pump and the loop filter is a voltage. ### Claim 15 (depends on 12) The method of claim 12, wherein the detector comprises a time to digital converter, the output from the loop filter comprises a digital word and the oscillator comprises a digital-controlled oscillator. ### Claim 16 (depends on 12) The method of claim 12, wherein the clock generation circuit further comprises a quadrature signal generator in communication with the output of the divider to generate the receive clock and the transmit clock. ### Claim 17 A clock generation circuit comprising: a receive clock generation circuit; a transmit clock generation circuit; and a signal source to provide a REFCLK signal; wherein the receive clock generation circuit and the transmit clock generation circuit each comprise: a phase locked loop, comprising: a detector to determine a difference between the REFCLK signal and a feedback signal and provide an output based on the difference; a loop filter to filter the output to create a filtered output; an oscillator to generate a clock signal with a frequency related to the filtered output; a divider to divide the clock signal by a quantity; and a multi-modulus divider in communication with an output of the divider, to further divide the output of the divider by an integer and supply the feedback signal to the detector; wherein the divider comprises a reset signal so as to be initialized to a known state; wherein the transmit clock is generated based on the output of the divider in the transmit clock generation circuit and the receive clock is generated based on the output of the divider in the receive clock generation circuit, and wherein a phase difference between the transmit clock and the receive clock is constant. ### Claim 18 (depends on 17) The clock generation circuit of claim 17, wherein at least one of the detector of the receive clock generation circuit or the detector of the transmit clock generation circuit comprises a phase/frequency detector and charge pump; and the oscillator comprises a voltage-controlled oscillator and the output from the phase/frequency detector and charge pump and the loop filter is a voltage. ### Claim 19 (depends on 17) The clock generation circuit of claim 17, wherein at least one of the detector of the receive clock generation circuit or the detector of the transmit clock generation circuit comprises a time to digital converter, the output from the loop filter comprises a digital word and the oscillator comprises a digital-controlled oscillator.