# US 11,444,626 B2 · Phase-locked loop slip detector

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- Number: US 11,444,626 B2
- Document ID: US11444626B2
- Status: Granted
- Kind: B2
- Application number: 17/458,001
- Filed: 2021-08-26
- Published: 2021-12-09
- Granted: 2022-09-13
- Earliest claimed: 2019-06-24
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Shailesh Ganapat Ghotgalkar; Wei Fu; Venkatseema Das; Jiankun Hu
- Web page: https://patentgrep.com/patent/US11444626B2

## CPC

- H03L 7/0891: {the up-down pulses controlling source and sink current generators, e.g. a charge pump}
- H03L 7/087: using at least two phase detectors or a frequency and phase detector in the loop
- H03L 7/095: using a lock detector (H03L7/087 takes precedence)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

A phase-locked loop (PLL) includes a phase-frequency detector (PFD) having a first PFD input, a second PFD input, and a PFD output. The PFD is configured to generate a first signal on the PFD output. The first signal comprises pulses having pulse widths indicative of a phase difference between signals on the first and second PFD inputs. A low pass filter (LPF) has an LPF input and an LPF output. The LPF input is coupled to the PFD output. A flip-flop has a clock input and a flip-flop output. The clock input is coupled to the LPF output. A lock-slip control circuit is coupled to the flip-flop output and to the first PFD input. The lock-slip control circuit is configured to determine phase-lock and phase-slip based at least in part on a signal on the flip-flop output.

## Claims

### Claim 1

A circuit, comprising:
a phase-locked loop (PLL) circuit; and
a lock-slip detect circuit coupled to the PLL, the lock-slip detect circuit including:
a low pass filter (LPF) having an LPF input and an LPF output;
a flip-flop having a flip-flop clock input and a flip-flop output, the flip-flop clock input coupled to the LPF output; and
a lock-slip control circuit coupled to the flip-flop output, wherein the lock-slip control circuit is configured to determine phase-lock, quasi phase-slip, and phase-slip of the PLL circuit.

### Claim 2 (depends on 1)

The circuit of claim 1, wherein:
the flip-flop has a flip-flop input, and wherein the PLL includes an inverter coupled between the flip-flop output and the flip-flop input.

### Claim 3 (depends on 1)

The circuit of claim 1, wherein:
the lock-slip control circuit receives a reference clock.

### Claim 4 (depends on 3)

The circuit of claim 3, wherein:
the lock-slip control circuit includes a counter circuit configured to count a number of edges on the flip-flop output in a predetermined number of cycles of the reference clock.

### Claim 5 (depends on 4)

The circuit of claim 4, wherein:
the lock-slip control circuit is configured to assert a lock signal indicating that the PLL is in phase-lock responsive to the number of edges being zero.

### Claim 6 (depends on 4)

The circuit of claim 4, wherein:
the lock-slip control circuit is configured to de-assert a lock signal indicating that the PLL is not in phase-lock responsive to the number of edges being greater than or equal to a first threshold number.

### Claim 7 (depends on 6)

The circuit of claim 6, wherein:
the lock-slip control circuit is configured to assert a quasi slip signal responsive to the number of edges being greater than a second threshold number and less than the first threshold number.

### Claim 8 (depends on 1)

The circuit of claim 1, wherein:
the flip-flop is coupled to a loop filter and a charge pump of the PLL circuit.

### Claim 9 (depends on 1)

The circuit of claim 1, wherein:
the LPF input is coupled to an output of a logic gate;
a first input of the logic gate is coupled to a first output of a phase-frequency detector (PFD); and
a second input of the logic gate is coupled to a second output of the PFD.

### Claim 10 (depends on 9)

The circuit of claim 9, wherein:
the logic gate is an OR gate.

### Claim 11 (depends on 9)

The circuit of claim 9, wherein:
the LPF includes a buffer having a resistance and a capacitance that determine a frequency response; and
the frequency response is configured to filter out signals from the logic gate having a pulse width below a pulse width threshold.

### Claim 12 (depends on 11)

The circuit of claim 11, wherein:
the capacitance includes a plurality of capacitors.

### Claim 13 (depends on 11)

The circuit of claim 11, wherein:
the capacitance includes a first capacitor, a second capacitor coupled to a first switch, and a third capacitor coupled to second switch.

### Claim 14 (depends on 13)

The circuit of claim 13, wherein:
the first switch and the second switch are configured to adjust the frequency response of the LPF.

### Claim 15 (depends on 13)

The circuit of claim 13, wherein:
the first switch and the second switch are controlled by a value stored in a configuration register.

### Claim 16 (depends on 1)

The circuit of claim 1, wherein:
the LPF is configured to filter signals having a pulse width less than or equal to 500 picoseconds.

### Claim 17

A system, comprising:
a low pass filter (LPF) having an LPF input and an LPF output;
a flip-flop having a flip-flop clock input and a flip-flop output, the flip-flop clock input coupled to the LPF output; and
a lock-slip control circuit coupled to the flip-flop output, wherein the lock-slip control circuit is configured to output an indicator indicating one of a phase-lock and a quasi phase-slip.

### Claim 18 (depends on 17)

The system of claim 17, further comprising:
an inverter having an inverter input coupled to the flip-flop output and an inverter output coupled to a flip-flop input of the flip-flop.

### Claim 19 (depends on 17)

The system of claim 17, wherein:
the lock-slip control circuit includes a counter circuit configured to count a number of edges on the flip-flop output in a predetermined number of cycles of a reference clock;
the lock-slip control circuit is configured to assert the indicator indicating that the PLL is in phase-lock responsive to the number of edges being zero; and
the lock-slip control circuit is configured to assert the indicator indicating quasi slip responsive to the number of edges being between a first threshold and a second threshold.

### Claim 20

A method for detecting slip in a phase-locked loop (PLL), comprising:
receiving, by a low pass filter (LPF), a signal from a phase-frequency detector (PFD);
filtering, by the LPF, the signal from the PFD to remove pulse widths below a first threshold to produce a filtered signal;
receiving, by a flip-flop, the filtered signal;
generating, by the flip-flop, a flip-flop output signal based on the filtered signal;
counting, by a lock-slip control circuit, a number of edges of the flip-flop output signal over a period of time;
in response to the number of edges of the flip-flop output signal being zero in the period of time, outputting, by the lock-slip control circuit, a phase-lock signal;
in response to the number of edges of the flip-flop output signal being between a second threshold and a third threshold, outputting, by the lock-slip control circuit, a quasi phase-slip signal; and
in response to the number of edges of the flip-flop output signal being at or greater than the third threshold, outputting, by the lock-slip control circuit, a phase-slip signal.