# US 11,444,624 B2 · Power management for multi-dimensional programmable logic devices

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- Number: US 11,444,624 B2
- Document ID: US11444624B2
- Status: Granted
- Kind: B2
- Application number: 17/074,245
- Filed: 2020-10-19
- Published: 2021-02-04
- Granted: 2022-09-13
- Earliest claimed: 2018-12-27
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Karthik Chandrasekar; Guang Chen; Wendemagegnehu T. Beyene; Ravi Prakash Gutala
- Web page: https://patentgrep.com/patent/US11444624B2

## CPC

- H03K 19/17772: for powering on or off
- G06F 30/34: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 90/00: Package configurations
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H02M 3/04: by static converters
- H02M 3/156: with automatic control of output voltage or current, e.g. switching regulators
- H10W 70/685: comprising multiple insulating layers
- H10W 72/07252: {changes in structures or sizes}
- H10W 72/07254: {changes in dispositions}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)

## Abstract

A device may include a fabric die coupled to an active interposer. The fabric die may include programmable logic fabric and configuration memory that programs the programmable logic fabric. The programmable logic fabric of the fabric die may access at least a portion of the active interposer to perform an operation. As discussed herein, different power management techniques associated with the active interposer may be used to improve operation of the device.

## Claims

### Claim 1

A system, comprising:
a tangible, non-transitory, and machine-readable medium, comprising machine-readable instructions stored thereon that, when executed by a processor, cause performance of operations comprising:
receiving an indication of a logic design;
identifying an expected resource consumption of the logic design;
placing the logic design in a system design for an integrated circuit based at least in part on the expected resource consumption of the logic design;
determining that resource consumption of the logic design changed; and
adjusting placement of the logic design within the system design based on the resource consumption.

### Claim 2 (depends on 1)

The system of claim 1, comprising a programmable logic device, wherein the operations comprise:
generating a bitstream based at least in part on the system design; and
transmitting the bitstream to the programmable logic device to program the logic design in programmable logic fabric of the programmable logic device.

### Claim 3 (depends on 1)

The system of claim 1, comprising:
an integrated circuit die comprising a first portion of a power distribution network; and
an active interposer circuit comprising a second portion of the power distribution network, wherein the active interposer circuit is configured to regulate the first portion of the power distribution network, the second portion of the power distribution network, or both, after the active interposer circuit is programmed based at least in part on the system design.

### Claim 4 (depends on 1)

The system of claim 1, wherein the operations comprise:
generating a bitstream based at least in part on the system design;
transmitting the bitstream to a programmable logic device to program the logic design in programmable logic fabric of the programmable logic device;
receiving an indication of a temperature from a thermal sensor of the programmable logic device; and
adjusting the system design based at least in part on the temperature.

### Claim 5 (depends on 1)

The system of claim 1, wherein the operations comprise:
programming a device based at least in part on the system design; and
transmitting a toggling factor to the device, wherein the device comprises a controller configured to tune an intrinsic capacitance of the device based at least in part on the toggling factor.

### Claim 6 (depends on 5)

The system of claim 5, wherein the device comprises an active interposer, and wherein the controller controls switching of components included within the active interposer based at least in part on toggling factor.

### Claim 7 (depends on 1)

The system of claim 1, comprising a device having a controller, wherein the controller is configured to generate an artificial current during a duration of time corresponding to low activity of the device, and wherein the operations comprise:
programming the device based at least in part on the system design; and
transmitting an indication of a current amount corresponding to the low activity of the device.

### Claim 8 (depends on 1)

The system of claim 1, comprising a programmable logic device, wherein the operations comprise:
programming the programmable logic device by writing a fabric configuration bitstream to configuration memory of the programmable logic device, where the fabric configuration bitstream is generated based at least in part on the system design.

### Claim 9 (depends on 8)

The system of claim 8, wherein writing the fabric configuration bitstream involves the fabric configuration bitstream transmitting from a base die to the configuration memory through interface circuitry of the programmable logic device, wherein the fabric configuration bitstream comprises configuration instructions associated with selectively activating a device within programmable logic fabric of the programmable logic device, and wherein selectively activating the device changes an intrinsic capacitance of the programmable logic fabric.

### Claim 10 (depends on 9)

The system of claim 9, wherein the configuration instructions are further associated with regulating noise using the intrinsic capacitance of the programmable logic fabric.

### Claim 11

A system, comprising:
a device having a controller, wherein the controller is configured to generate an artificial current during a duration of time corresponding to low activity of the device; and
a tangible, non-transitory, and machine-readable medium, comprising machine-readable instructions stored thereon that, when executed by a processor, cause performance of operations comprising:
receiving an indication of a logic design;
identifying an expected resource consumption of the logic design;
placing the logic design in a system design for an integrated circuit based at least in part on the expected resource consumption of the logic design;
programming the device based at least in part on the system design; and
transmitting an indication of a current amount corresponding to the low activity of the device.

### Claim 12 (depends on 11)

The system of claim 11, wherein the operations comprise:
transmitting a toggling factor to the device, wherein the controller is configured to tune an intrinsic capacitance of the device based at least in part on the toggling factor.

### Claim 13 (depends on 12)

The system of claim 12, wherein the device comprises an active interposer, and wherein the controller controls switching of components included within the active interposer based at least in part on toggling factor.

### Claim 14 (depends on 11)

The system of claim 11, wherein the operations comprise:
programming the device by writing a fabric configuration bitstream to configuration memory of the device, where the fabric configuration bitstream is generated based at least in part on the system design.

### Claim 15

A system, comprising:
a tangible, non-transitory, and machine-readable medium, comprising machine-readable instructions stored thereon that, when executed by a processor, cause performance of operations comprising:
receiving an indication of a logic design;
identifying an expected resource consumption of the logic design;
placing the logic design in a system design for an integrated circuit based at least in part on the expected resource consumption of the logic design;
generating a bitstream based at least in part on the system design;
transmitting the bitstream to a programmable logic device to program the logic design in programmable logic fabric of the programmable logic device;
receiving an indication of a temperature from a thermal sensor of the programmable logic device; and
adjusting the system design based at least in part on the temperature.

### Claim 16 (depends on 15)

The system of claim 15, wherein the operations comprise:
programming a device based at least in part on the system design; and
transmitting a toggling factor based on the temperature to the device, wherein the device comprises a controller configured to tune an intrinsic capacitance of the device based at least in part on the toggling factor.

### Claim 17 (depends on 16)

The system of claim 16, wherein the device comprises an active interposer, and wherein the controller controls switching of components included within the active interposer based at least in part on toggling factor.

### Claim 18 (depends on 15)

The system of claim 15, comprising a device having a controller, wherein the controller is configured to generate an artificial current during a duration of time corresponding to low activity of the device, and wherein the operations comprise:
programming the device based at least in part on the system design; and
transmitting an indication of a current amount corresponding to the low activity of the device.

### Claim 19 (depends on 15)

The system of claim 15, comprising the programmable logic device, wherein the operations comprise:
programming the programmable logic device by writing a fabric configuration bitstream to configuration memory of the programmable logic device, where the fabric configuration bitstream is generated based at least in part on the system design.

### Claim 20 (depends on 19)

The system of claim 19, wherein writing the fabric configuration bitstream involves the fabric configuration bitstream transmitting from a base die to the configuration memory through interface circuitry of the programmable logic device, wherein the fabric configuration bitstream comprises configuration instructions associated with selectively activating a device within the programmable logic fabric of the programmable logic device, and wherein selectively activating the device changes an intrinsic capacitance of the programmable logic fabric.