# US 11,444,619 B2 · Driving circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,444,619 B2 - Document ID: US11444619B2 - Status: Granted - Kind: B2 - Application number: 17/402,708 - Filed: 2021-08-16 - Published: 2022-03-10 - Granted: 2022-09-13 - Earliest claimed: 2020-09-07 - Assignees: Changxin Memory Technologies, Inc. - Applicants: Changxin Memory Technologies, Inc. - Inventors: Liang Zhang - Web page: https://patentgrep.com/patent/US11444619B2 ## CPC - H03K 17/6872: {using complementary field-effect transistors} - G11C 7/1057: {Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load} - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - G11C 11/4076: Timing circuits (for regeneration management G11C11/406) - H03K 5/133: using a chain of active delay devices - H03K 17/08122: {in field-effect transistor switches} - H03K 17/284: in field effect transistor switches - G11C 11/4063: Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing - H03K 2005/00019: {Variable delay} - H03K 2005/00078: {Fixed delay} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A driving circuit, including: a pull-up transistor and a pull-down transistor, where a first terminal of the pull-up transistor is connected with a power source, a second terminal of the pull-up transistor is connected with a first terminal of the pull-down transistor to together output a driving signal, and a second terminal of the pull-down transistor is connected to ground; and a control circuit connected with a control terminal of the pull-up transistor and/or the pull-down transistor respectively and configured to control the on or off switching of the pull-up transistor and/or the pull-down transistor so as to change the driving signal. The pull-up transistor and the pull-down transistor are not switched on at the same time under the control of the control circuit. ## Claims ### Claim 1 A driving circuit, comprising: a pull-up transistor and a pull-down transistor, wherein a first terminal of the pull-up transistor is connected with a power source, a second terminal of the pull-up transistor is connected with a first terminal of the pull-down transistor to commonly output a driving signal, and a second terminal of the pull-down transistor is connected to ground; and a control circuit connected with a control terminal of at least one of the pull-up transistor or the pull-down transistor respectively and configured to control on or off switching of at least one of the pull-up transistor or the pull-down transistor so as to change the driving signal, wherein the pull-up transistor and the pull-down transistor are not switched on at the same time under the control of the control circuit, wherein the driving circuit further comprises: a delay circuit connected with the control circuit and configured to receive an input signal and perform a preset delay on the input signal to generate a delayed input signal, wherein both the input signal and the delayed input signal are input to the control circuit, wherein the control circuit is further configured to receive the driving signal and selectively output the input signal or the delayed input signal according to the driving signal, to control the pull-up transistor and the pull-down transistor to be switched on or switched off sequentially according to a preset sequence. ### Claim 2 (depends on 1) The driving circuit of claim 1, wherein the control circuit comprises: a pull-up control circuit connected with the control terminal of the pull-up transistor and configured to control the on or off switching of the pull-up transistor; and a pull-down control circuit connected with the control terminal of the pull-down transistor and configured to control the on or off switching of the pull-down transistor. ### Claim 3 (depends on 2) The driving circuit of claim 2, wherein the pull-up control circuit comprises a first selection circuit, wherein an input terminal of the first selection circuit is configured to receive the input signal, the other input terminal of the first selection circuit is configured to receive the delayed input signal, a control terminal of the first selection circuit is configured to receive the driving signal, and an output terminal of the first selection circuit is connected with the control terminal of the pull-up transistor; and the pull-down control circuit comprises a second selection circuit, wherein an input terminal of the second selection circuit is configured to receive the input signal, the other input terminal of the second selection circuit is configured to receive the delayed input signal, a control terminal of the second selection circuit is configured to receive the driving signal, and an output terminal of the second selection circuit is connected with the control terminal of the pull-down transistor. ### Claim 4 (depends on 3) The driving circuit of claim 3, wherein the first selection circuit and the second selection circuit each comprises two transmission gates, wherein a control terminal of the transmission gate is configured to input the driving signal, the other control terminal of the transmission gate is configured to input an inverted signal of the driving signal, and the signals input by the two control terminals of the transmission gate are configured to commonly control the switching-on or switching-off of the transmission gate. ### Claim 5 (depends on 1) The driving circuit of claim 1, wherein the pull-up transistor is an N-type transistor or a P-type transistor, and the pull-down transistor is an N-type transistor. ### Claim 6 (depends on 1) The driving circuit of claim 1, wherein the pull-up transistor is defined to switch from a switched-off state to a switched-on state at time t1, and the pull-down transistor is defined to switch from a switched-on state to a switched-off state at time t2, wherein in a process that the pull-down transistor is switched off and the pull-up transistor is switched on, the time t2 is earlier than the time t1. ### Claim 7 (depends on 1) The driving circuit of claim 1, wherein the pull-up transistor is defined to switch from a switched-on state to a switched-off state at time t3, and the pull-down transistor is defined to switch from a switched-off state to a switched-on state at time t4, wherein in a process that the pull-up transistor is switched off and the pull-down transistor is switched on, the time t3 is earlier than the time t4. ### Claim 8 (depends on 1) The driving circuit of claim 1, wherein a start time at which a signal input by the control terminal of the pull-up transistor is converted from a high level to a low level is defined as t5, and a start time at which a signal input by the control terminal of the pull-down transistor is converted from a high level to a low level is defined as t6, wherein in a process that the pull-down transistor is switched off and the pull-up transistor is switched on, the start time t6 is earlier than the start time t5. ### Claim 9 (depends on 1) The driving circuit of claim 1, wherein a start time at which a signal input by the control terminal of the pull-up transistor is converted from a low level to a high level is defined as t7, and a start time at which a signal input by the control terminal of the pull-down transistor is converted from a low level to a high level is defined as t8, wherein in a process that the pull-up transistor is switched off and the pull-down transistor is switched on, the start time t7 is earlier than the start time t8. ### Claim 10 (depends on 1) The driving circuit of claim 1, wherein the delay circuit is a fixed delay chain. ### Claim 11 (depends on 10) The driving circuit of claim 10, wherein the fixed delay chain comprises an even number of inverters connected in series. ### Claim 12 (depends on 1) The driving circuit of claim 1, wherein the delay circuit is a variable delay chain.