# US 11,444,618 B2 · High-side switch and low-side switch loss equalization in a multiphase switching converter > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,444,618 B2 - Document ID: US11444618B2 - Status: Granted - Kind: B2 - Application number: 16/707,160 - Filed: 2019-12-09 - Published: 2020-06-11 - Granted: 2022-09-13 - Earliest claimed: 2018-12-11 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Manu Balakrishnan - Web page: https://patentgrep.com/patent/US11444618B2 ## CPC - H02M 7/53871: {with automatic control of output voltage or current} - H03K 17/56: by the use, as active elements, of semiconductor devices (using diodes H03K17/74) - H02M 7/2173: {in a biphase or polyphase circuit arrangement (H02M7/2176 takes precedence; voltage multipliers H02M7/25)} - H02M 7/5395: by pulse-width modulation - H03K 4/06: having triangular shape - H03K 7/08: Duration or width modulation {; Duty cycle modulation} - H02M 1/327: {against abnormal temperatures} - H02M 7/53873: {with digital control} - H03K 2017/0806: {against excessive temperature} - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract An electrical system includes a motor and a plurality of switch pairs, each switch pair having a high-side switch, a low-side switch, and a switch node coupled to the motor. The electrical system also includes gate driver circuitry coupled to each switch of the plurality of switch pairs. The electrical system also includes a controller coupled to the gate driver circuitry. The controller is configured to direct the gate driver circuitry to provide a first set of gate drive signals together with (i.e., overlapping pulses) a second set of gate drive signals, wherein the first set of gate drive signals is phase-shifted relative to the second set of gate drive signals. ## Claims ### Claim 1 An electrical system, comprising: a plurality of switch pairs, each switch pair having a high-side switch, a low-side switch, and a switch terminal configured to be coupled to a motor; gate driver circuitry coupled to each switch of the plurality of switch pairs; and a controller coupled to the gate driver circuitry, wherein the controller is coupled to the gate driver circuitry providing a first set of gate drive signals together with a second set of gate drive signals, wherein the first set of gate drive signals is phase-shifted relative to the second set of gate drive signals; wherein the first set of gate drive signals includes a high-side gate drive signal with a first duty-cycle D and a low-side gate drive signal with a complementary duty-cycle (1-D) relative to the first duty-cycle, and wherein the second set of gate drive signals includes a high-side gate drive signal with the complementary duty-cycle and a low-side gate drive signal with the first duty-cycle; wherein the first duty-cycle D is not equal to the complementary duty-cycle (1-D). ### Claim 2 (depends on 1) The electrical system of claim 1, wherein the controller is configured to direct the gate driver circuitry to provide the first set of gate drive signals and the second set of gate drive signals to each of the plurality of switch pairs in different 120 degree intervals of a 360 degree control cycle, wherein the different 120 degree intervals are spaced from each other by 60 degrees. ### Claim 3 (depends on 1) The electrical system of claim 1, wherein the controller is configured to select the first duty-cycle and the complementary duty-cycle of gate drive signals based on a target pulse-width modulation (PWM) frequency and a target performance parameter. ### Claim 4 (depends on 3) The electrical system of claim 3, wherein the target performance parameter is one of a target winding current of the motor and a target voltage switching duty-cycle of the motor. ### Claim 5 (depends on 3) The electrical system of claim 3, wherein the controller comprises a digital timer or counter configured to provide an up-down ramp with an upper threshold and a lower threshold, wherein the controller selects the first duty-cycle and the complementary duty-cycle of gate drive signals based on the upper and lower thresholds, and wherein the upper and lower thresholds are selected based on a target voltage switching duty-cycle of the motor. ### Claim 6 A multiphase switching converter controller method, comprising: generating a first set of gate drive signals; generating a second set of gate drive signals, wherein the first set of gate drive signals is phase-shifted relative to the second set of gate drive signals; providing a first set of gate drive signals to a first switch pair of a three-phase inverter; and providing a second set of gate drive signals to a second switch pair of the three-phase inverter while the first set of gate drive signals are being provided to the first switch pair; wherein generating the first set of gate drive signals comprises: generating a first high-side gate drive signal with a first duty-cycle D; and generating a first low-side gate drive signal with a complementary duty-cycle (1-D) relative to the first duty-cycle, and wherein generating the second set of gate drive signals comprises: generating a second high-side gate drive signal with the complementary duty-cycle (1-D); and generating a second low-side gate drive signal with the first duty-cycle D; wherein the first duty-cycle D is not equal to the complementary duty-cycle (1-D). ### Claim 7 (depends on 6) The method of claim 6, wherein generating the first set of gate drive signals and generating the second set of gate drive signals are based on a digital up-down timer or counter circuit, an upper threshold, and a lower threshold. ### Claim 8 (depends on 6) The method of claim 6, wherein generating the first set of gate drive signals involves a first analog comparator with a triangular wave input and a first threshold input, and wherein generating the second set of gate drive signals involves a second analog comparator with the triangular wave input and a second threshold input.