# US 11,444,612 B2 · Comparator low power response

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- Number: US 11,444,612 B2
- Document ID: US11444612B2
- Status: Granted
- Kind: B2
- Application number: 17/223,097
- Filed: 2021-04-06
- Published: 2021-07-22
- Granted: 2022-09-13
- Earliest claimed: 2019-04-08
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Nitin Agarwal; Venkat Ramakrishna Saripalli; Venkata Ramanan R
- Web page: https://patentgrep.com/patent/US11444612B2

## CPC

- H03F 3/45183: {Long tailed pairs (H03F3/4521, H03F3/45237 take precedence)}
- H03K 5/2481: {with at least one differential stage}
- H03F 1/0205: {in transistor amplifiers}
- H03F 3/45179: {using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence)}
- H03F 3/45659: {Controlling the loading circuit of the differential amplifier}
- H03F 2200/456: A scaled replica of a transistor being present in an amplifier
- H03F 2203/45008: the addition of two signals being made by a resistor addition circuit for producing the common mode signal
- H03F 2203/45652: the LC comprising one or more further dif amp stages, either identical to the dif amp or not, in cascade
- H03F 2203/45674: the LC comprising one current mirror
- H03F: AMPLIFIERS
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

In described examples, an amplifier can be arranged to generate a first stage output signal in response to an input signal. The input signal can be coupled to control a first current coupled from a first current source through a common node to generate the first stage output signal. A replica circuit can be arranged to generate a replica load signal in response to the input signal and in response to current received from the common node. A current switch can be arranged to selectively couple a second current from a second current source to the common node in response to the replica load signal.

## Claims

### Claim 1

A circuit comprising:
a differential input that includes a first input and a second input;
an amplifier stage that includes a first set of input transistors coupled to a common node, wherein the first set of input transistors includes a first transistor that includes a gate coupled to the first input, and a second transistor that includes a gate coupled to the second input;
a second set of input transistors coupled between the common node and a replica node, wherein the second set of input transistors includes a third transistor that includes a gate coupled to the first input, and a fourth transistor that includes a gate coupled to the second input;
a bias generator coupled to the replica node and a bias node; and
a current switch that includes a fifth transistor that includes a gate coupled to the bias node, wherein the fifth transistor is coupled to the common node.

### Claim 2 (depends on 1)

The circuit of claim 1, wherein the bias generator includes:
a current source coupled to the bias node;
a sixth transistor coupled between the bias node and the replica node; and
a seventh transistor coupled between the replica node and a ground node.

### Claim 3 (depends on 1)

The circuit of claim 1, wherein the current switch includes a resistor coupled between a voltage node and the fifth transistor.

### Claim 4 (depends on 1)

The circuit of claim 1, wherein:
the amplifier stage further includes a differential output that includes a first output and a second output;
the first transistor is coupled between the common node and the first output; and
the second transistor is coupled between the common node and the second output.

### Claim 5 (depends on 4)

The circuit of claim 4, wherein the amplifier stage further includes:
a first resistor coupled between the first output and a divided voltage node; and
a second resistor coupled between the second output and the divided voltage node.

### Claim 6 (depends on 5)

The circuit of claim 5, wherein the amplifier stage further includes:
a sixth transistor coupled between the first output and a ground node; and
a seventh transistor coupled between the second output and the ground node.

### Claim 7 (depends on 6)

The circuit of claim 6, wherein:
the six transistor includes a gate coupled to the divided voltage node; and
the seventh transistor includes a gate coupled to the divided voltage node.

### Claim 8 (depends on 4)

The circuit of claim 4, wherein:
the amplifier stage is a first amplifier stage; and
the circuit further comprises a second amplifier stage coupled to the differential output of the first amplifier stage.

### Claim 9 (depends on 8)

The circuit of claim 8, wherein the second amplifier stage further includes:
a sixth transistor that includes a gate coupled to the first output of the first amplifier stage; and
a seventh transistor that includes a gate coupled to the second output of the first amplifier stage.

### Claim 10 (depends on 9)

The circuit of claim 9, wherein the second amplifier stage further includes:
an eighth transistor coupled between a voltage node and the sixth transistor; and
a ninth transistor coupled between the voltage node and the seventh transistor.

### Claim 11 (depends on 1)

The circuit of claim 1, further comprising a current source coupled to the common node.

### Claim 12

A circuit comprising:
a differential input;
an amplifier stage that includes a first set of input transistors coupled to a common node;
a replica input transistor pair coupled to the common node and the differential input, the replica input transistor pair configured to:
detect a voltage drop on the common node; and
provide a replica signal based on the voltage drop on the common node;
a bias generator coupled to the replica input transistor pair and configured to:
receive the replica signal; and
provide a bias signal based on the replica signal; and
a current switch coupled to the bias generator and to the common node and configured to:
receive the bias signal, and
provide current to the common node based on the bias signal.

### Claim 13 (depends on 12)

The circuit of claim 12, wherein:
the differential input includes a first input and second input;
the first set of input transistors includes:
a first transistor that includes a gate coupled to the first input; and
a second transistor that includes a gate coupled to the second input; and
the replica input transistor pair includes:
a third transistor that includes a gate coupled to the first input; and
a fourth transistor that includes a gate coupled to the second input.

### Claim 14 (depends on 13)

The circuit of claim 13, wherein each of the first, second, third, and fourth transistors is coupled to the common node.

### Claim 15 (depends on 13)

The circuit of claim 13, wherein the third and fourth transistors are coupled between the common node and a replica node to provide the replica signal at the replica node.

### Claim 16 (depends on 15)

The circuit of claim 15, wherein the bias generator includes:
a current source;
a fifth transistor coupled between the current source and the replica node; and
a sixth transistor coupled between the fifth transistor and a ground node.

### Claim 17 (depends on 16)

The circuit of claim 16, wherein the current switch includes:
a resistor coupled to a voltage node; and
a seventh transistor coupled between the resistor and the common node, wherein the seventh transistor includes a gate coupled to the current source and to the fifth transistor.

### Claim 18 (depends on 13)

The circuit of claim 13, wherein the amplifier stage further includes:
a first resistor coupled between the first transistor and a divided voltage node; and
a second resistor coupled between the second transistor and the divided voltage node.

### Claim 19 (depends on 18)

The circuit of claim 18, wherein the amplifier stage further includes:
a fifth transistor coupled between the first transistor and a ground node; and
a sixth transistor coupled between the second transistor and the ground node.

### Claim 20 (depends on 12)

The circuit of claim 12, further comprising a current source coupled to the common node.