# US 11,444,608 B2 · Level shifter > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,444,608 B2 - Document ID: US11444608B2 - Status: Granted - Kind: B2 - Application number: 17/366,592 - Filed: 2021-07-02 - Published: 2021-10-28 - Granted: 2022-09-13 - Earliest claimed: 2018-08-10 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Chien-Yuan Chen; Cheng Hung Lee; Hung-Jen Liao; Hau-Tai Shieh - Web page: https://patentgrep.com/patent/US11444608B2 ## CPC - H03K 3/356156: {with synchronous operation} - H03K 3/356191: {with synchronous operation} - G11C 7/1084: {Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load} - G11C 7/1087: {Data input latches} - G11C 11/417: for memory cells of the field-effect type - G11C 11/5621: {using charge storage in a floating gate} - H03K 17/6871: {the output circuit comprising more than one controlled field-effect transistor} - H03K 19/018521: {of complementary type, e.g. CMOS} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A level shifter includes: a first inverter configured to receive an input signal in a low voltage domain and shift the input signal from the low voltage domain to a first output signal at a first output terminal in a high voltage domain higher than the low voltage domain in response to a logical high state of a first clock signal in the low voltage domain; a second inverter configured to receive a complement of the input signal and shift the complement of the input signal from the low voltage domain to a second output signal at a second output terminal in the high voltage domain in response to the logical high state; a first NMOS sensing transistor and a second NMOS sensing transistor; a PMOS transistor configured to equalize the first output signal and the second output signal in response to a logical low state of the first clock signal. ## Claims ### Claim 1 A level shifter comprising: a first inverter configured to receive an input signal in a low voltage domain and shift the input signal from the low voltage domain to a first output signal at a first output terminal in a high voltage domain higher than the low voltage domain in response to a logical high state of a first clock signal in the low voltage domain; a second inverter configured to receive a complement of the input signal and shift the complement of the input signal from the low voltage domain to a second output signal at a second output terminal in the high voltage domain in response to the logical high state of the first clock signal; a first NMOS sensing transistor and a second NMOS sensing transistor having a common source terminal, wherein a drain terminal of the first NMOS sensing transistor is coupled to the first inverter, a gate terminal of the first NMOS sensing transistor is configured to receive the input signal, a drain terminal of the second NMOS sensing transistor is coupled to the second inverter, and a gate terminal of the second NMOS sensing transistor is configured to receive the complement of the input signal; and a PMOS transistor coupled between the first output terminal and the second output terminal and having a gate terminal connected to receive the first clock signal in the low voltage domain, the PMOS transistor configured to equalize the first output signal and the second output signal in response to a logical low state of the first clock signal. ### Claim 2 (depends on 1) The level shifter of claim 1, wherein the PMOS transistor is configured to equalize the first output signal and the second output signal to a predetermined voltage level. ### Claim 3 (depends on 2) The level shifter of claim 2, wherein the predetermined voltage level is half of a second input voltage in the high voltage domain. ### Claim 4 (depends on 1) The level shifter of claim 1, further comprising a third inverter operating in the low voltage domain and configured to create the complement of the input signal. ### Claim 5 (depends on 1) The level shifter of claim 1, further comprising an NMOS transistor connected between the common source terminal and ground and having a gate terminal connected to receive the first clock signal. ### Claim 6 (depends on 1) The level shifter of claim 1, wherein a level of the low voltage domain is less than 40% of a level of the high voltage domain. ### Claim 7 A level shifting system, comprising: a first inverter configured to receive an input signal in a low voltage domain and shift the input signal from the low voltage domain to a first output signal at a first output terminal in a high voltage domain higher than the low voltage domain in response to a logical high state of a first clock signal in the low voltage domain; a second inverter configured to receive a complement of the input signal and shift the complement of the input signal from the low voltage domain to a second output signal at a second output terminal in the high voltage domain in response to the logical high state of the first clock signal; a first NMOS sensing transistor and a second NMOS sensing transistor having a common source terminal, wherein a drain terminal of the first NMOS sensing transistor is coupled to the first inverter, a gate terminal of the first NMOS sensing transistor is configured to receive the input signal, a drain terminal of the second NMOS sensing transistor is coupled to the second inverter, and a gate terminal of the second NMOS sensing transistor is configured to receive the complement of the input signal; a PMOS transistor coupled between the first output terminal and the second output terminal and having a gate terminal connected to receive the first clock signal in the low voltage domain, the PMOS transistor configured to equalize the first output signal and the second output signal in response to a logical low state of the first clock signal; and a latch circuit configured to latch the second output signal in the high voltage domain in response to a second clock signal, wherein the second clock signal and the first clock signal are in phase with one another. ### Claim 8 (depends on 7) The level shifting system of claim 7, wherein the PMOS transistor is configured to equalize the first output signal and the second output signal to a predetermined voltage level. ### Claim 9 (depends on 8) The level shifting system of claim 8, wherein the predetermined voltage level is half of a second input voltage in the high voltage domain. ### Claim 10 (depends on 7) The level shifting system of claim 7, further comprising a third inverter operating in the low voltage domain and configured to create the complement of the input signal. ### Claim 11 (depends on 7) The level shifting system of claim 7, wherein a level of the low voltage domain is less than 40% of a level of the high voltage domain. ### Claim 12 (depends on 7) The level shifting system of claim 7, wherein the latch circuit latches the second output signal when the first clock signal is in the logical low state. ### Claim 13 (depends on 7) The level shifting system of claim 7, wherein the latch circuit comprising: a first tri-state inverter configured to invert the second output signal in the high voltage domain in response to the second clock signal; a fourth inverter coupled between the first tri-state inverter and a latch circuit output terminal and configured to reinvert the inverted second output signal in the high voltage domain; and a second tri-state inverter coupled between the first tri-state inverter and the latch circuit output terminal and configured to bypass the fourth inverter in response to the second clock signal. ### Claim 14 (depends on 13) The level shifting system of claim 13, wherein when the second clock signal is at a logic low state of the second clock signal, the first tri-state inverter inverts the second output signal in the high voltage domain and the second tri-state inverter is turned off. ### Claim 15 (depends on 13) The level shifting system of claim 13, wherein when the second clock signal is at a logic high state of the second clock signal, the first tri-state inverter latches the second output signal in the high voltage domain and the second tri-state inverter is turned on to bypass the fourth inverter. ### Claim 16 A level shifting method, comprising: receiving a first clock signal having a logic high state and a logic low state in a low voltage domain; equalizing a first output signal at a first output terminal and a second output signal at a second output terminal in response to the logic low state of the first clock signal, the first output signal and the second output signal being in a high voltage domain higher than the low voltage domain; receiving an input signal in the low voltage domain; and outputting the first output signal at the first output terminal and the second output signal at the second output terminal based on the input signal and a complement of the input signal respectively in response to the logic high state of the first clock signal. ### Claim 17 (depends on 16) The level shifting method of claim 16, further comprising: latching the second output signal in the high voltage domain in response to a second clock signal, wherein the first clock signal and the second clock signal are in phase with one another. ### Claim 18 (depends on 17) The level shifting method of claim 17, wherein the second clock signal is in the high voltage domain. ### Claim 19 (depends on 16) The level shifting method of claim 16, further comprising: connecting the first output terminal and the second output terminal through a PMOS transistor, the PMOS transistor having a gate terminal connected to receive the first clock signal. ### Claim 20 (depends on 16) The level shifting method of claim 16, further comprising: inverting the input signal to the first output signal; and inverting the complement of the input signal to the second output signal.