# US 11,444,606 B2 · Spike pulse generation circuit comprising single silicon device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,444,606 B2 - Document ID: US11444606B2 - Status: Granted - Kind: B2 - Application number: 17/168,395 - Filed: 2021-02-05 - Published: 2022-01-06 - Granted: 2022-09-13 - Earliest claimed: 2020-07-01 - Assignees: Korea University Research and Business Foundation - Applicants: Korea University Research and Business Foundation - Inventors: Sang Sig Kim; Kyoung Ah Cho; Doo Hyeok Lim - Web page: https://patentgrep.com/patent/US11444606B2 ## CPC - H03K 3/0315: {Ring oscillators} - H10D 18/00: Thyristors - H10D 64/27: Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates - H10W 99/00: Subject matter not provided for in other groups of this subclass - B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic - H10D 12/211: {Gated diodes} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES ## Abstract Provided is a spike pulse generation circuit comprising a single silicon device configured to non-periodically or periodically generate a spike pulse. More particularly, the spike pulse generation circuit comprising the single silicon device can utilize a positive feedback loop and a negative feedback loop to be mutually connected so as to selectively output a spike pulse related to a neural oscillation function similar to biological oscillation, thereby being capable of serving as a ring oscillator and performing a neuron function operation. ## Claims ### Claim 1 A spike pulse generation circuit comprising a single silicon device, wherein a positive feedback loop is generated in the single silicon device when a potential generated by an input voltage exceeds; a threshold value, resulting in a selectively generated spike pulse having an initial state, and each of spike pulses corresponding to the generated potential is selectively generated and output according to a generated firing event, and the selectively generated spike pulse is reset; the initial state when a negative feedback loop is triggered in the single silicon device based on the generated firing event. ### Claim 2 (depends on 1) The spike pulse generation circuit comprising the single silicon device according to claim 1, wherein the spike pulse generation circuit integrates the input voltage in a channel region of the single silicon device to generate the potential. ### Claim 3 (depends on 2) The spike pulse generation circuit comprising the single silicon device according to claim 2, wherein the channel region comprises an n-doped first channel region and a p-doped second channel region, and a potential well for accumulating charge carriers is formed in the channel region to integrate the input voltage in the channel region, wherein, when the input voltage is applied, holes are integrated in or recombined with the second channel region. ### Claim 4 (depends on 3) The spike pulse generation circuit comprising the single silicon device according to claim 3, wherein the channel region comprises a potential barrier, and injection of charge carriers is blocked before the potential exceeds the threshold. ### Claim 5 (depends on 4) The spike pulse generation circuit comprising the single silicon device according to claim 4, wherein a height of the potential barrier is lowered as the holes are integrated in the second channel region to generate the positive feedback loop so that the channel region operates the potential barrier to be removed only for a predetermined time. ### Claim 6 (depends on 1) The spike pulse generation circuit comprising the single silicon device according to claim 1, wherein the single silicon device is set to a latch-up state when the positive feedback loop is generated, and is set to a latch-down state when the negative feedback loop is triggered. ### Claim 7 (depends on 6) The spike pulse generation circuit comprising the single silicon device according to claim 6, wherein a voltage of the single silicon device in the latch-up state is reduced due to internal resistance to trigger the negative feedback loop. ### Claim 8 (depends on 7) The spike pulse generation circuit comprising the single silicon device according to claim 7, wherein the single silicon device generates the positive feedback loop when a ratio of a composite resistance comprising the internal resistance in the latch-down state and first and second resistors to a combination of the input voltage and the internal resistance in the latch-down state is equal to or greater than a latch-up voltage. ### Claim 9 (depends on 7) The spike pulse generation circuit comprising the single silicon device according to claim 7, wherein the single silicon device generates the negative feedback loop when a ratio of a composite resistance comprising the internal resistance in the latch-up state and first and second resistors to a combination of the input voltage and the internal resistance in the latch-up state is less than or equal to a latch-down voltage. ### Claim 10 (depends on 1) The spike pulse generation circuit comprising the single silicon device according to claim 1, wherein a magnitude and fire rate of the spike pulse increase as a magnitude of the input voltage increases. ### Claim 11 (depends on 1) The spike pulse generation circuit comprising the single silicon device according to claim 1, wherein an interval between the spike pulses is changed according to a magnitude of the input voltage.