# US 11,444,605 B2 · Spike generation circuit, information processing circuit, power conversion circuit, detector, and electronic circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,444,605 B2 - Document ID: US11444605B2 - Status: Granted - Kind: B2 - Application number: 17/408,599 - Filed: 2021-08-23 - Published: 2022-01-13 - Granted: 2022-09-13 - Earliest claimed: 2019-02-28 - Assignees: Japan Science and Technology Agency - Applicants: Japan Science and Technology Agency - Inventors: Takeaki Yajima - Web page: https://patentgrep.com/patent/US11444605B2 ## CPC - H03K 3/02: Generators characterised by the type of circuit or by the means used for producing pulses (H03K3/64 - H03K3/84 take precedence) - H03K 3/354: Astable circuits - G06G 7/60: for living beings, e.g. their nervous systems {; for problems in the medical field} - G06N 3/063: using electronic means - H03K 5/01: Shaping pulses (discrimination against noise or interference H03K5/125) - H03K 5/156: Arrangements in which a continuous pulse train is transformed into a train having a desired pattern - H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) - H03K 2005/00013: {Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G06G: ANALOGUE COMPUTERS (analogue optical computing devices G06E3/00) - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS ## Abstract A spike generation circuit includes a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node that is an intermediate node coupled to an input terminal to which an input signal is input, a switch connected in series with the first CMOS inverter, between the first power supply and the second power supply, a first inverting circuit that outputs an inversion signal of a signal of the first node to a control terminal of the switch, and a delay circuit that delays the signal of the first node, outputs a delayed signal to an input node of the first CMOS inverter, and outputs an isolated output spike signal to an output terminal. ## Claims ### Claim 1 A spike generation circuit comprising: a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node that is an intermediate node coupled to an input terminal to which an input signal is input; a switch connected in series with the first CMOS inverter, between the first power supply and the second power supply; a first inverting circuit that outputs an inversion signal of a signal of the first node to a control terminal of the switch; and a delay circuit that delays the signal of the first node, outputs a delayed signal to an input node of the first CMOS inverter, and outputs an isolated output spike signal to an output terminal. ### Claim 2 (depends on 1) The spike generation circuit according to claim 1, wherein the first inverting circuit outputs the inversion signal of the signal of the first node to the control terminal of the switch and a second node, and wherein the delay circuit includes the first inverting circuit, and a second inverting circuit that outputs an inversion signal of a signal of the second node to the input node of the first CMOS inverter and a third node coupled to the output terminal. ### Claim 3 (depends on 2) The spike generation circuit according to claim 2, wherein the first inverting circuit includes an odd number of second CMOS inverters connected in an odd number of stages between the first node and the second node, an input node of each of the odd number of second CMOS inverters being coupled to the first node, an output node of each of the odd number of second CMOS inverters being coupled to the second node, and wherein the second inverting circuit includes an odd number of third CMOS inverters connected in an odd number of stages between the second node and the third node, an input node of each of the odd number of third CMOS inverters being coupled to the second node, an output node of each of the odd number of third CMOS inverters being coupled to the third node. ### Claim 4 (depends on 3) The spike generation circuit according to claim 3, wherein the second inverting circuit includes three or more odd number of third CMOS inverters. ### Claim 5 (depends on 4) The spike generation circuit according to claim 4, further comprising a first capacitance element having a first end coupled to a fourth node and a second end coupled to a first reference potential terminal, the fourth node being between any adjacent two of the three or more third CMOS inverters. ### Claim 6 (depends on 5) The spike generation circuit according to claim 5, wherein a capacitance value of the first capacitance element is equal to or greater than a gate capacitance value of one FET in the three or more third CMOS inverters. ### Claim 7 (depends on 1) The spike generation circuit according to claim 1, further comprising a second capacitance element having a first end coupled to the first node and a second end coupled to a second reference potential terminal. ### Claim 8 (depends on 1) The spike generation circuit according to claim 1, wherein a voltage of the second power supply is higher than a voltage of the first power supply, and wherein the switch is an N-channel transistor and is connected between the first node and the first power supply, or the switch is a P-channel transistor and is connected between the first node and the second power supply. ### Claim 9 (depends on 1) The spike generation circuit according to claim 1, further comprising a voltage conversion circuit that is provided between the input terminal and the intermediate terminal and outputs, to the intermediate node, a signal obtained by converting a voltage of the input signal, wherein the delay circuit does not output the isolated output spike signal when the voltage of the input signal is within a predetermined range. ### Claim 10 (depends on 1) The spike generation circuit according to claim 1, further comprising a time constant circuit that is provided between the input terminal and the intermediate node and increases a time constant of a rise of the input signal, and outputs a resulting signal to the intermediate node, wherein the delay circuit outputs the isolated output spike signal after a delay time relating to a time constant of the time constant circuit after the input signal is input. ### Claim 11 (depends on 1) The spike generation circuit according to claim 1, further comprising an input circuit that is provided between the input terminal and the intermediate node and increases or decreases a voltage of the intermediate node when an input spike signal is input as the input signal, wherein the delay circuit outputs the isolated output spike signal when a frequency with which the input spike signal is input becomes within a predetermined range. ### Claim 12 (depends on 1) The spike generation circuit according to claim 1, further comprising an input circuit that is provided between the input terminal and the intermediate node and varies a voltage of the intermediate node according to an amount of change in the input signal with respect to time, wherein the delay circuit outputs the isolated output spike signal when the amount of change in the input signal with respect to time becomes within a predetermined range. ### Claim 13 (depends on 1) An information processing circuit comprising: the spike generation circuit according to claim 1; a condition setting circuit that processes an input signal and outputs a processed signal to the spike generation circuit to set a condition for the spike generation circuit to output the isolated output spike signal; and a spike processing circuit that processes the isolated output spike signal output by the spike generation circuit. ### Claim 14 (depends on 1) A power conversion circuit comprising: a switch element; and a control circuit that includes the spike generation circuit according to claim 1, and controls on and off of the switch element. ### Claim 15 A spike generation circuit comprising: a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node; a first switch connected in series with the first CMOS inverter, between the first power supply and the second power supply; an inverting circuit that outputs an inversion signal of a signal of the first node to a control terminal of the first switch; a delay circuit that delays the signal of the first node, outputs a delayed signal to an input node of the first CMOS inverter, and outputs an isolated outputs spike signal to an output terminal; and an intermediate node provided in the inverting circuit and coupled to an input terminal to which an input signal is input. ### Claim 16 (depends on 15) The spike generation circuit according to claim 15, wherein the first CMOS inverter outputs a first level, which is one of a high level and a low level, and outputs a second level, which is the other of the high level and the low level, wherein the first switch is turned on when the first level is input to a control terminal, and turned off when the second level is input to the control terminal, wherein the inverting circuit includes a first inverting circuit and a second inverting circuit, the first inverting circuit being configured to output the first level to the control terminal of the first switch when the first node changes from the first level to the second level, the second inverting circuit being configured to output the second level to the control terminal of the first switch when an output of the delay circuit becomes the second level, and wherein the intermediate node is provided in the second inverting circuit. ### Claim 17 (depends on 16) The spike generation circuit according to claim 16, wherein the second inverting circuit includes a second switch that has a control terminal coupled to an output of the delay circuit and connects the intermediate node to a power supply, to which an initial level of the input signal is supplied, when the delay circuit outputs the second level. ### Claim 18 (depends on 17) The spike generation circuit according to claim 17, wherein the first inverting circuit includes a third switch that has a control terminal coupled to the first node and connects the control terminal of the first switch to a power supply, to which the first level is supplied, when the first node becomes at the second level. ### Claim 19 (depends on 16) The spike generation circuit according to claim 16, further comprising a fourth switch that has a control terminal coupled to the control terminal of the first switch and connects the first node to a power supply, to which the first level is supplied, when the control terminal of the first switch is at the second level. ### Claim 20 (depends on 15) The spike generation circuit according to claim 15, further comprising a second CMOS inverter having an input node coupled to the intermediate node and an output node coupled to the control terminal of the first switch. ### Claim 21 (depends on 15) The spike generation circuit according to claim 15, further comprising a voltage conversion circuit that is provided between the input terminal and the intermediate terminal and outputs, to the intermediate node, a signal obtained by converting a voltage of the input signal, wherein the delay circuit does not output the isolated output spike signal when the voltage of the input signal is within a predetermined range. ### Claim 22 (depends on 15) The spike generation circuit according to claim 15, further comprising a time constant circuit that is provided between the input terminal and the intermediate node and increases a time constant of a rise of the input signal, and outputs a resulting signal to the intermediate node, wherein the delay circuit outputs the isolated output spike signal after a delay time relating to a time constant of the time constant circuit after the input signal is input. ### Claim 23 (depends on 15) The spike generation circuit according to claim 15, further comprising an input circuit that is provided between the input terminal and the intermediate node and increases or decreases a voltage of the intermediate node when an input spike signal is input as the input signal, wherein the delay circuit outputs the isolated output spike signal when a frequency with which the input spike signal is input becomes within a predetermined range. ### Claim 24 (depends on 15) The spike generation circuit according to claim 15, further comprising an input circuit that is provided between the input terminal and the intermediate node and varies a voltage of the intermediate node according to an amount of change in the input signal with respect to time, wherein the delay circuit outputs the isolated output spike signal when the amount of change in the input signal with respect to time becomes within a predetermined range. ### Claim 25 (depends on 15) An information processing circuit comprising: the spike generation circuit according to claim 15; a condition setting circuit that processes an input signal and outputs a processed signal to the spike generation circuit to set a condition for the spike generation circuit to output the isolated output spike signal; and a spike processing circuit that processes the isolated output spike signal output by the spike generation circuit. ### Claim 26 (depends on 15) A power conversion circuit comprising: a switch element; and a control circuit that includes the spike generation circuit according to claim 15, and controls on and off of the switch element. ### Claim 27 A spike generation circuit comprising: a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node that is an intermediate node coupled to an input terminal to which an input signal is input; a capacitance element having a first end coupled to the first node and a second end coupled to a reference potential terminal, an electric charge by the input signal being accumulated in the capacitance element; and a delay circuit that includes an even number of second CMOS inverters connected in an even number of stages between the first node and an output terminal, an input node of each of the even number of second CMOS inverters being coupled to the first node, an output node of each of the even number of second CMOS inverters being coupled to the output terminal, the delay circuit outputting an isolated output spike signal to the output terminal by outputting a signal to reset a charge accumulated in the capacitance element to an input node of the first CMOS inverter to cause a voltage of the first node to fall when the voltage of the first node becomes a predetermined value, wherein the even number of second CMOS inverters are six or more even number of second CMOS inverters. ### Claim 28 (depends on 27) The spike generation circuit according to claim 27, further comprising a voltage conversion circuit that is provided between the input terminal and the intermediate terminal and outputs, to the intermediate node, a signal obtained by converting a voltage of the input signal, wherein the delay circuit does not output the isolated output spike signal when the voltage of the input signal is within a predetermined range. ### Claim 29 (depends on 27) The spike generation circuit according to claim 27, further comprising a time constant circuit that is provided between the input terminal and the intermediate node and increases a time constant of a rise of the input signal, and outputs a resulting signal to the intermediate node, wherein the delay circuit outputs the isolated output spike signal after a delay time relating to a time constant of the time constant circuit after the input signal is input. ### Claim 30 (depends on 27) The spike generation circuit according to claim 27, further comprising an input circuit that is provided between the input terminal and the intermediate node and increases or decreases a voltage of the intermediate node when an input spike signal is input as the input signal, wherein the delay circuit outputs the isolated output spike signal when a frequency with which the input spike signal is input becomes within a predetermined range. ### Claim 31 (depends on 27) The spike generation circuit according to claim 27, further comprising an input circuit that is provided between the input terminal and the intermediate node and varies a voltage of the intermediate node according to an amount of change in the input signal with respect to time, wherein the delay circuit outputs the isolated output spike signal when the amount of change in the input signal with respect to time becomes within a predetermined range. ### Claim 32 (depends on 27) An information processing circuit comprising: the spike generation circuit according to claim 27; a condition setting circuit that processes an input signal and outputs a processed signal to the spike generation circuit to set a condition for the spike generation circuit to output the isolated output spike signal; and a spike processing circuit that processes the isolated output spike signal output by the spike generation circuit. ### Claim 33 (depends on 27) A power conversion circuit comprising: a switch element; and a control circuit that includes the spike generation circuit according to claim 27, and controls on and off of the switch element. ### Claim 34 A spike generation circuit comprising: a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node that is an intermediate node coupled to an input terminal to which an input signal is input; a capacitance element having a first end coupled to the first node and a second end coupled to a reference potential terminal, an electric charge by the input signal being accumulated in the capacitance element; a delay circuit that includes an even number of second CMOS inverters connected in an even number of stages between the first node and an output terminal, an input node of each of the even number of second CMOS inverters being coupled to the first node, an output node of each of the even number of second CMOS inverters being coupled to the output terminal, the delay circuit outputting an isolated output spike signal to the output terminal by outputting a signal to reset a charge accumulated in the capacitance element to an input node of the first CMOS inverter to cause a voltage of the first node to fall when the voltage of the first node becomes a predetermined value; and a switch that is connected in series with the first CMOS inverter between the first power supply and the second power supply and includes a control terminal to which a signal of an output node of an odd-numbered second CMOS inverter from the first node among the even number of second CMOS inverters is input. ### Claim 35 A spike generation circuit comprising: a time constant circuit that includes a capacitor, which has a first end coupled to an output node and a second end coupled to a first reference potential terminal, and a constant current element or constant current circuit, which has a first end coupled to an input terminal to which an input signal of which a voltage depends on time is input and a second end coupled to the output node and generates a constant current corresponding to a voltage difference between the first end and the second end, the time constant circuit increasing a time constant of a rise of the input signal, and outputting a resulting signal to an intermediate node from the output node; and an output circuit that outputs an isolated output spike signal to an output terminal and resets a voltage of the intermediate node in response to the voltage of the intermediate node becoming a threshold voltage, wherein the output circuit outputs the isolated output spike signal after a delay time relating to a time constant of the time constant circuit after the input signal is input, and wherein the constant current element or constant current circuit includes a diode connected in a backward direction or a transistor having a control terminal to which a voltage is applied so that the transistor is in an on-state. ### Claim 36 A spike generation circuit comprising: a time constant circuit that includes a capacitor, which has a first end coupled to an output node and a second end coupled to a first reference potential terminal, and a constant current circuit, which has a first end coupled to an input terminal to which an input signal of which a voltage depends on time is input and a second end coupled to the output node and generates a constant current corresponding to a voltage difference between the first end and the second end, the time constant circuit increasing a time constant of a rise of the input signal, and outputting a resulting signal to an intermediate node from the output node; and an output circuit that outputs an isolated output spike signal to an output terminal and resets a voltage of the intermediate node in response to the voltage of the intermediate node becoming a threshold voltage, wherein the constant current circuit is a current mirror circuit including: a first transistor having a current input terminal and a current output terminal, one of the current input terminal and the current output terminal being coupled to the input terminal, the other of the current input terminal and the current output terminal being coupled to the output node, and a second transistor having a current input terminal, a current output terminal, and a control terminal, one of the current input terminal and the current output terminal being coupled to the input terminal through a first diode connected in a forward direction, the other of the current input terminal and the current output terminal being coupled to a second reference potential terminal through a second diode connected in a backward direction, the control terminal being coupled to a control terminal of the first transistor. ### Claim 37 A spike generation circuit comprising: a capacitor having a first end coupled to an intermediate node and a second end coupled to a first reference potential terminal; a voltage conversion circuit that includes a first element and a second element connected in series between an input terminal, to which an input signal of which a voltage depends on time is input, and a second reference potential terminal, and a resistance element having a first end coupled to a node, which is between the first element and the second element, and a second end coupled to the intermediate node, and outputs, to the intermediate node, a signal obtained by dividing a voltage of the input signal by the first element and the second element; and an output circuit that outputs an isolated output spike signal to an output terminal and resets a voltage of the intermediate node in response to the voltage of the intermediate node becoming a threshold voltage, wherein a product of a resistance value of the resistance element and a capacitance value of the capacitor is greater than a width of the isolated output spike signal. ### Claim 38 (depends on 37) The spike generation circuit according to claim 37, wherein the first element is one of a resistor, a diode, and a transistor, and the second element is one of a resistor, a diode, and a transistor.