# US 11,444,532 B2 · Non-linear clamp strength tuning method and apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,444,532 B2 - Document ID: US11444532B2 - Status: Granted - Kind: B2 - Application number: 16/727,759 - Filed: 2019-12-26 - Published: 2021-07-01 - Granted: 2022-09-13 - Earliest claimed: 2019-12-26 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Xiaosen Liu; Krishnan Ravichandran; Harish Krishnamurthy; Vivek De - Web page: https://patentgrep.com/patent/US11444532B2 ## CPC - G05F 1/563: including two stages of regulation at least one of which is output level responsive, e.g. coarse and fine regulation - H02M 3/158: including plural semiconductor devices as final control devices for a single load - G05F 1/571: with overvoltage detector - G05F 1/575: characterised by the feedback circuit - G05F 1/59: including plural semiconductor devices as final control devices for a single load - H02M 1/088: for the simultaneous control of series or parallel connected semiconductor devices - H02N 13/00: Clutches or holding devices using electrostatic attraction, e.g. using Johnson-Rahbek effect - H03L 5/00: Automatic control of voltage, current, or power - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - H02N: ELECTRIC MACHINES NOT OTHERWISE PROVIDED FOR - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) ## Abstract A 3-level ripple quantization scheme provides power transistor (MOS) strength-tuning mechanism focused on the transient clamp period. The 3-level ripple quantization scheme solves the digital low dropout's (D-LDO's) tradeoff between silicon area (e.g., decoupling capacitor size), quiescent power consumption (e.g., speed of comparators), wide load range, and optimal output ripple. The 3-level ripple quantization scheme eliminates oscillation risk from either wide dynamic range or parasitic by exploiting asynchronous pulse patterns. As such, ripple magnitude for both fast di/dt loading events and various steady-state scenarios are shrunk effectively, resulting significant efficiency benefits. ## Claims ### Claim 1 An apparatus comprising: a first comparator to compare an output voltage or a divided version of the output voltage on an output power supply rail with a first reference, wherein the first comparator is to generate a first output; a second comparator to compare the output voltage or a divided version of the output voltage on the output power supply rail with a second reference, wherein the second comparator is to generate a second output; a third comparator to compare the output voltage or a divided version of the output voltage on the output power supply rail with a third reference, wherein the third comparator is to generate a third output; power gates coupled to the output power supply rail; a first controller to receive the first and second outputs and to generate a code indicative of a coarse setting for power gates; and a second controller to receive the first, second, and third outputs, wherein the second controller is to generate a fine code for the power gates; wherein the first reference has a voltage level below a voltage level of the second reference, and wherein the third reference has a voltage level below the voltage level of the first reference. ### Claim 2 (depends on 1) The apparatus of claim 1, further comprising a gating logic to receive the coarse and fine codes, and to generate a two dimensional code to enable power gates, wherein the power gates are arranged in an array configuration. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the array configuration is a thermometer array. ### Claim 4 (depends on 2) The apparatus of claim 2, wherein the array configuration is a binary array. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the first output when asserted indicates that the output voltage is below the first reference, wherein the second output when asserted indicates that the output voltage is above the second threshold, and wherein the third output when asserted indicates that the output voltage is below the third reference. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the second controller provides non-linear strength tuning of the power gates, wherein the first controller provides linear strength tuning of the power gates. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the second controller comprises a pattern detector, which generates a pulse when the first and second outputs appear in a staggered order indicative of an oscillation of the output voltage. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein the second controller further comprises a filter coupled to an output of the pattern detector to filter the pulse from noise. ### Claim 9 (depends on 8) The apparatus of claim 8, wherein the second controller further comprises a shift register coupled to the output of the filter, wherein the shift register generates the fine code dynamically. ### Claim 10 An apparatus comprising: a first comparator to compare an output voltage or a divided version of the output voltage on an output power supply rail with a first reference, wherein the first comparator is to generate a first output; a second comparator to compare the output voltage or a divided version of the output voltage on the output power supply rail with a second reference, wherein the second comparator is to generate a second output; a third comparator to compare the output voltage or a divided version of the output voltage on the output power supply rail with a third reference, wherein the third comparator is to generate a third output; power gates coupled to the output power supply rail; a first controller to receive the first and second outputs and to generate a first code for linear strength tuning of the power gates; and a second controller to receive the first, second, and third outputs, wherein the second controller is to generate a second code for non-linear strength tuning of the power gates, and wherein the second controller comprises a pattern detector that generates a pulse when the first and second outputs appear in a staggered order indicative of an oscillation of the output voltage. ### Claim 11 (depends on 10) The apparatus of claim 10, wherein the second controller further comprises a filter coupled to an output of the pattern detector to filter the pulse from noise. ### Claim 12 (depends on 11) The apparatus of claim 11, wherein the second controller further comprises a shift register coupled to the output of the filter, wherein the shift register generates the non-linear code dynamically. ### Claim 13 A system comprising: a memory; a processor core coupled to the memory; a digital low dropout (D-LDO) regulator to receive an input power supply voltage and to generate an output power supply voltage on an output power supply rail for the processor core, wherein the D-LDO comprises: a 3-level ripple quantization circuitry to generate first, second, and third outputs in accordance with first, second, and third reference voltages, respectively; power gates coupled to the output power supply rail; a first controller to receive the first and second outputs and to generate a first code for linear strength tuning of the power gates; and a second controller to receive the first, second, and third outputs, wherein the second controller is to generate a second code for non-linear strength tuning of the power gates, and wherein the second controller comprises a pattern detector which generates a pulse when the first and second outputs appear in a staggered order indicative of an oscillation of the output voltage; and a wireless interface to allow the processor to communicate with another device. ### Claim 14 (depends on 13) The system of claim 13, wherein the second controller further comprises a filter coupled to an output of the pattern detector to filter the pulse from noise. ### Claim 15 (depends on 14) The system of claim 14, wherein the second controller further comprises a shift register coupled to the output of the filter, wherein the shift register generates the non-linear code dynamically. ### Claim 16 (depends on 13) The system of claim 13, wherein the D-LDO comprises a gating logic to receive the linear and non-linear codes, and to generate a two dimensional code to enable power gates, wherein the power gates are arranged in an array configuration. ### Claim 17 (depends on 16) The system of claim 16, wherein the array configuration is one of a thermometer array or a binary array. ### Claim 18 An apparatus comprising: a first comparator to compare an output voltage or a divided version of the output voltage on an output power supply rail with a first reference, wherein the first comparator is to generate a first output; a second comparator to compare the output voltage or a divided version of the output voltage on the output power supply rail with a second reference, wherein the second comparator is to generate a second output; a third comparator to compare the output voltage or a divided version of the output voltage on the output power supply rail with a third reference, wherein the third comparator is to generate a third output; power gates coupled to the output power supply rail; a first controller to receive the first and second outputs and to generate a code indicative of a coarse setting for power gates; and a second controller to receive the first, second, and third outputs, wherein the second controller is to generate a fine code for the power gates, and wherein the second controller comprises a pattern detector, which generates a pulse when the first and second outputs appear in a staggered order indicative of an oscillation of the output voltage. ### Claim 19 (depends on 18) The apparatus of claim 18, wherein the second controller comprises a filter coupled to an output of the pattern detector to filter the pulse from noise. ### Claim 20 (depends on 19) The apparatus of claim 19, wherein the second controller comprises a shift register coupled to the output of the filter, wherein the shift register generates the fine code dynamically. ### Claim 21 (depends on 18) The apparatus of claim 18, further comprising a gating logic to receive the coarse and fine codes, and to generate a two dimensional code to enable power gates, wherein the power gates are arranged in an array configuration. ### Claim 22 (depends on 18) The apparatus of claim 18, wherein the first output when asserted indicates that the output voltage is below the first reference, wherein the second output when asserted indicates that the output voltage is above the second threshold, and wherein the third output when asserted indicates that the output voltage is below the third reference.