# US 11,444,455 B2 · Integrated circuit protection

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- Number: US 11,444,455 B2
- Document ID: US11444455B2
- Status: Granted
- Kind: B2
- Application number: 16/873,112
- Filed: 2020-02-03
- Published: 2020-08-13
- Granted: 2022-09-13
- Earliest claimed: 2019-02-09
- Applicants: Eugene Robert Worley
- Inventors: Eugene Robert Worley
- Web page: https://patentgrep.com/patent/US11444455B2

## CPC

- H02H 9/046: {responsive to excess voltage appearing at terminals of integrated circuits}
- H10D 1/43: Resistors having PN junctions
- H10D 89/611: {using diodes as protective elements}
- H10D 89/711: {using bipolar transistors as protective elements}
- H10D 89/713: {including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices}
- H10D 89/911: {using passive elements as protective elements}
- H10D 8/25: Zener diodes
- H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

In certain aspects of the disclosure, a protection circuit includes a first input/output (I/O) pin, a second I/O pad, a shunt clamp coupled to the first I/O pad, and a resistor coupled between the shunt clamp and the second I/O pad. The resistor has a first dynamic resistance at a voltage of 100 millivolts across the resistor, the resistor has a second dynamic resistance at a voltage of three volts across the resistor, and the second dynamic resistance is at least five times greater than the first dynamic resistance.

## Claims

### Claim 1

A system, comprising:
a shunt clamp;
an integrated circuit; and
a resistor coupled between the shunt clamp and the integrated circuit, wherein the resistor has a first dynamic resistance at a voltage of 100 millivolts across the resistor, the resistor has a second dynamic resistance at a voltage of three volts across the resistor, the second dynamic resistance is at least five times greater than the first dynamic resistance, and the resistor comprises:
a first N+ region on a substrate;
a second N+ region on the substrate; and
an N-well on the substrate, wherein at least a portion of the N-well is disposed between the first N+ region and the second N+ region, and a depth of the N-well is less than a depth of the first N+ region and less than a depth of the second N+ region.

### Claim 2 (depends on 1)

The system of claim 1, wherein the second dynamic resistance is at least ten times greater than the first dynamic resistance.

### Claim 3 (depends on 1)

The system of claim 1, further comprising a connector configured to detachably connect to a cable, a memory card, or a subscriber identification module (SIM) card, wherein the resistor is coupled between the connector and the integrated circuit.

### Claim 4 (depends on 1)

The system of claim 1, wherein the shunt clamp comprises a silicon controlled rectifier (SCR).

### Claim 5 (depends on 1)

The system of claim 1, wherein the shunt clamp comprises a Zener diode.

### Claim 6 (depends on 1)

The system of claim 1, wherein the shunt clamp comprises a snap-back bipolar transistor.

### Claim 7 (depends on 1)

The system of claim 1, wherein the substrate is a P-type substrate.

### Claim 8 (depends on 1)

The system of claim 1, wherein a length of the N-well between the first N+ region and the second N+ region is equal to or less than 2.5 microns.

### Claim 9 (depends on 1)

The system of claim 1, wherein an N-type doping density of the N-well is equal to or less than 1017/cm3.

### Claim 10 (depends on 1)

The system of claim 1, wherein the resistor further comprises:
one or more first contacts coupled to the first N+ region;
a first metal terminal coupled to the one or more first contacts;
one or more second contacts coupled to the second N+ region; and
a second metal terminal coupled to the one or more second contacts.

### Claim 11

An electrostatic discharge (ESD) protection circuit, comprising:
a first input/output (I/O) pin;
a second I/O pin;
a shunt clamp coupled to the first I/O pin; and
a resistor coupled between the shunt clamp and the second I/O pin, wherein the resistor has a first dynamic resistance at a voltage of 100 millivolts across the resistor, the resistor has a second dynamic resistance at a voltage of three volts across the resistor, the second dynamic resistance is at least five times greater than the first dynamic resistance, and the resistor comprises:
a first N+ region on a substrate;
a second N+ region on the substrate; and
an N-well on the substrate, wherein at least a portion of the N-well is disposed between the first N+ region and the second N+ region, and a depth of the N-well is less than a depth of the first N+ region and less than a depth of the second N+ region.

### Claim 12 (depends on 11)

The protection circuit of claim 11, wherein the second dynamic resistance is at least ten times greater than the first dynamic resistance.

### Claim 13 (depends on 11)

The protection circuit of claim 11, wherein the shunt clamp comprises a silicon controlled rectifier (SCR).

### Claim 14 (depends on 11)

The protection circuit of claim 11, wherein the shunt clamp comprises a Zener diode.

### Claim 15 (depends on 11)

The protection circuit of claim 11, wherein the shunt clamp comprises a snap-back bipolar transistor.

### Claim 16 (depends on 11)

The protection circuit of claim 11, wherein the resistor further comprises:
one or more first contacts coupled to the first N+ region;
a first metal terminal coupled to the one or more first contacts;
one or more second contacts coupled to the second N+ region; and
a second metal terminal coupled to the one or more second contacts.