# US 11,444,429 B2 · Light source for integrated silicon photonics

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- Number: US 11,444,429 B2
- Document ID: US11444429B2
- Status: Granted
- Kind: B2
- Application number: 17/169,037
- Filed: 2021-02-05
- Published: 2021-08-26
- Granted: 2022-09-13
- Earliest claimed: 2020-02-25
- Assignees: Marvell Asia Pte Ltd
- Applicants: Marvell Asia Pte, Ltd.
- Inventors: Xiaoguang He; Radhakrishnan L. Nagarajan
- Web page: https://patentgrep.com/patent/US11444429B2

## CPC

- H01S 5/0042: {On wafer testing, e.g. lasers are tested before separating wafer into chips}
- H01S 5/0207: {Substrates having a special shape}
- G01R 31/2635: {Testing light-emitting diodes, laser diodes or photodiodes}
- G02B 6/12004: {Combinations of two or more optical elements}
- H01S 5/021: {Silicon based substrates}
- H01S 5/02315: Support members, e.g. bases or carriers
- H01S 5/0234: Up-side down mountings, e.g. Flip-chip, epi-side down mountings or junction down mountings
- H01S 5/02345: Wire-bonding
- H01S 5/323: in AIIIBV compounds, e.g. AlGaAs-laser, {InP-based laser}
- H04B 10/07: Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems
- H04B 10/27: Arrangements for networking
- G01R 31/2831: {Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates (G01R31/318511 takes precedence; testing during manufacture H10P74/00)}
- G02B 6/4245: {Mounting of the opto-electronic elements}
- G02B 6/4274: {Electrical aspects (G02B6/4263 and G02B6/4265 take precedence)}
- G02B 2006/12061: {Silicon}
- G02B 2006/12121: {Laser}
- H01S 5/0201: {Separation of the wafer into individual elements, e.g. by dicing, cleaving, etching or directly during growth}
- H01S 5/0237: by soldering
- H01S 5/0239: Combinations of electrical or optical elements
- H01S 5/042: Electrical excitation {; Circuits therefor (monolithically integrated laser drive components H01S5/0261)}
- H01S 5/04257: {having positive and negative electrodes on the same side of the substrate}
- H01S 5/12: the resonator having a periodic structure, e.g. in distributed feedback [DFB] lasers (comprising a photonic bandgap structure H01S5/11; surface-emitting lasers H01S5/18)
- H01S 5/4018: {Lasers electrically in series}
- H01S: DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G02B: OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- H04B: TRANSMISSION

## Abstract

A photonics device includes a silicon wafer including an upper surface region, a trench region, and a ridge structure. The ridge structure electrically isolates the upper surface region from the trench region. A laser diode chip flip-bonded onto the silicon wafer includes an electrode region bonded with the upper surface region, a gain region bonded with the trench region, and an isolation region bonded with the ridge structure. The isolation region electrically isolates the gain region from the electrode region. A conductor layer arranged between the silicon wafer and the laser diode chip includes a first section electrically connecting the gain region to a first electrode of the photonics device and a second section configured to electrically connect the electrode region to a second electrode of the photonics device. The first section is electrically isolated from the second section by the isolation region.

## Claims

### Claim 1

A method for forming a photonics device, the method comprising:
defining a silicon wafer having an upper surface region, a trench region, and a ridge structure located between the upper surface region and the trench region, the ridge structure being configured to electrically isolate the upper surface region from the trench region;
flip-bonding a laser diode chip onto the silicon wafer, ther laser diode chip comprising a gain region bonded to the trench region, an electrode region bonded to the upper surface region, and an isolation region between the electrode region and the gain region, the isolation region configured to electrically isolate the gain region from the electrode region; and
arranging a conductor layer between the silicon wafer and the laser diode chip, the conductor layer including a first section configured to electrically connect the gain region to an anode electrode of the photonics device and a second section configured to electrically connect the electrode region to a cathode electrode of the photonics device, the first section being electrically isolated from the second section by the isolation region.

### Claim 2 (depends on 1)

The method of claim 1, wherein the laser diode chip comprises a laser based on electrical pumped gain media including a distributed feedback (DFB) laser formed in an indium-phosphide substrate.

### Claim 3 (depends on 1)

The method of claim 1, wherein defining the silicon wafer comprises laying an under-bump metallization layer in the trench region and forming a solder bump over the under-bump metallization layer.

### Claim 4 (depends on 3)

The method of claim 3, wherein the gain region comprises an active layer, a first contact metal layer overlying active layer, and a bond pad formed on the first contact metal layer, the method further comprising; bonding the bond pad to the solder bump in the trench region.

### Claim 5 (depends on 4)

The method of claim 4, wherein defining the silicon wafer further comprises preparing the upper surface region by forming a silicon layer on an insulator layer over the silicon wafer, forming an under-bump metallization layer on the silicon layer, and forming a solder bump on the under-bump metallization layer.

### Claim 6 (depends on 5)

The method of claim 5, wherein the electrode region comprises a second contact metal layer, the method further comprising bonding the second contact metal layer to the solder bump in the upper surface region.

### Claim 7 (depends on 5)

The method of claim 5, further comprising forming a silicon layer on an insulator layer over the ridge structure and engaging an active layer in the isolation region with the silicon layer, the active layer in the isolation region being separated from the active layer in the gain region by a first gap.

### Claim 8 (depends on 7)

The method of claim 7, wherein the trench region comprises a second gap between the upper surface region and the ridge structure,.

### Claim 9 (depends on 3)

The method of claim 3, wherein arranging the conductor layer comprises forming a first section of the conductor layer connecting with the under-bump metallization layer under the gain region and a second section of the conductor layer connecting with the under-bump metallization layer under the electrode region.

### Claim 10 (depends on 9)

The method of claim 9, wherein arranging the conductor layer further comprises forming patterned linear extensions of the conductor layer as virtual wires to connect the cathode electrode of a first die of the photonics device to an anode electrode of a next die of the photonics device.

### Claim 11 (depends on 10)

The method of claim 10, further comprising using the virtual wires to interconnect one or more rows or columns of laser diode chips on respective chip sites the photonics device for wafer-level burn-in and testing of the photonics device.

### Claim 12 (depends on 1)

The method of claim 1, further comprising forming at least a second ridge structure substantially in parallel to the ridge structure and using the second ridge structure for passively aligning the laser diode chip with the-at least one chip site.

### Claim 13

A photonics device, comprising:
a silicon wafer including (i) an upper surface region, (ii) a trench region, and (iii) a ridge structure formed between the upper surface region and the trench region, the ridge structure being configured to electrically isolate the upper surface region from the trench region;
a laser diode chip flip-bonded onto the silicon wafer, the laser diode chip including (i) an electrode region bonded with the upper surface region, (ii) a gain region bonded with the trench region, and (iii) an isolation region between the electrode region and the gain region and bonded with the ridge structure, the isolation region configured to electrically isolate the gain region from the electrode region; and
a conductor layer arranged between the silicon wafer and the laser diode chip, the conductor layer including a first section configured to electrically connect the gain region of the laser diode chip to a first electrode of the photonics device and a second section configured to electrically connect the electrode region to a second electrode of the photonics device, the first section being electrically isolated from the second section by the isolation region.

### Claim 14 (depends on 13)

The photonics device of claim 13, wherein the silicon wafer includes a plurality of chip sites and the laser diode chip is bonded to one of the plurality of chip sites.

### Claim 15 (depends on 14)

The photonics device of claim 14, further comprising a plurality of the laser diode chips bonded to respective ones of the plurality of chip sites.

### Claim 16 (depends on 13)

The photonics device of claim 13, wherein the upper surface region and an upper surface of the ridge structure are coplanar.

### Claim 17 (depends on 16)

The photonics device of claim 16, wherein the trench region is not coplanar with the upper surface region.

### Claim 18 (depends on 13)

The photonics device of claim 13, wherein a p-side of the laser diode chip faces the silicon wafer and an n-side of the laser diode chip faces away from the silicon wafer.

### Claim 19 (depends on 13)

The photonics device of claim 13, wherein the first electrode is an anode electrode and the second electrode is a cathode electrode.

### Claim 20 (depends on 19)

The photonics device of claim 19, further comprising a first under-bump metallization later arranged in the trench region below the first section of the conductor layer and a second under-bump metallization layer arranged in the upper surface region below the second section of the conductor layer.