# US 11,444,237 B2 · Spin orbit torque (SOT) memory devices and methods of fabrication

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- Number: US 11,444,237 B2
- Document ID: US11444237B2
- Status: Granted
- Kind: B2
- Application number: 16/024,393
- Filed: 2018-06-29
- Published: 2020-01-02
- Granted: 2022-09-13
- Earliest claimed: 2018-06-29
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Noriyuki Sato; Tanay Gosavi; Gary Allen; Sasikanth Manipatruni; Kaan Oguz; Kevin O'Brien; Christopher Wiegand; Angeline Smith; Tofizur Rahman; Ian Young; Ben Buford
- Web page: https://patentgrep.com/patent/US11444237B2

## CPC

- G11C 11/18: using Hall-effect devices
- H10N 50/80: Constructional details
- G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell}
- G11C 11/1673: {Reading or sensing circuits or methods}
- G11C 11/1675: {Writing or programming circuits or methods}
- H01F 10/3254: {the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ]}
- H01F 10/329: {Spin-exchange coupled multilayers wherein the magnetisation of the free layer is switched by a spin-polarised current, e.g. spin torque effect}
- H10B 61/00: Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10N 50/01: Manufacture or treatment
- H10N 50/10: Magnetoresistive devices
- H10N 50/85: Materials of the active region
- G11C 11/14: using thin-film elements
- H01F 10/3286: {Spin-exchange coupled multilayers having at least one layer with perpendicular magnetic anisotropy}
- H10B 61/22: {of the field-effect transistor [FET] type}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01F: MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A spin orbit torque (SOT) memory device includes a SOT electrode having a spin orbit coupling material. The SOT electrode has a first sidewall and a second sidewall opposite to the first sidewall. The SOT memory device further includes a magnetic tunnel junction device on a portion of the SOT electrode. A first MTJ sidewall intersects the first SOT sidewall and a portion of the first MTJ sidewall and the SOT sidewall has a continuous first slope. The MTJ device has a second sidewall that does not extend beyond the second SOT sidewall and at least a portion of the second MTJ sidewall has a second slope.

## Claims

### Claim 1

A memory array structure, comprising:
a first SOT electrode and a second SOT electrode, wherein the first and second SOT electrodes each have a length in a first direction and a width in a second direction, orthogonal to the first direction, and wherein the first and second SOT electrodes are separated from each other by an intervening space along the second direction;
a first MTJ structure over a first portion of the length of the first SOT electrode;
a second MTJ structure over a first portion of the length of the second SOT electrode, wherein the first portions of the lengths of the first and second SOT electrodes are substantially equal;
a first dielectric material layer adjacent to a first sidewall portion of the first MTJ structure and adjacent to a first sidewall portion of the second MTJ structure, wherein the first dielectric material layer occupies the space and has a width substantially equal to the first portions of the lengths; and
a second dielectric material layer adjacent to a second sidewall portion of both the first and second MTJ structures, wherein the second dielectric material layer is over a second portion of the length of the first SOT electrode, and over a second portion of the length of the second SOT electrode, and wherein the second dielectric material layer is adjacent to a sidewall of the first dielectric material layer.

### Claim 2 (depends on 1)

The memory array structure of claim 1, wherein the first portion of the lengths comprises a center portion of the SOT electrodes, and wherein the second portion of the lengths of the SOT electrode comprises an end portion of the SOT electrodes.

### Claim 3 (depends on 1)

The memory array structure of claim 1, wherein the first dielectric material layer is adjacent to a sidewall of the first portion of the lengths of the first and second SOT electrodes.

### Claim 4 (depends on 3)

The memory array structure of claim 3, wherein:
the first dielectric material layer is adjacent to a sidewall of the second portion of the length of the first SOT electrode; and
the first dielectric material layer is adjacent to a sidewall of the second portion of the length of the second SOT electrode.

### Claim 5 (depends on 4)

The memory array structure of claim 4, wherein the second dielectric material layer is over the first dielectric material layer that is adjacent to a sidewall of the second portion of the lengths of the first and second SOT electrodes.

### Claim 6 (depends on 1)

The memory array structure of claim 1, wherein the first dielectric material layer and the second dielectric material layer have substantially the same material composition.

### Claim 7 (depends on 1)

The memory array structure of claim 1, wherein the first dielectric material layer and the second dielectric material layer have different material compositions.

### Claim 8 (depends on 1)

The memory array structure of claim 1, wherein each of the first MTJ structure and the second MTJ structure has a first pair parallel sidewalls adjacent to the first dielectric material layer, and wherein the first and second MTJ structures have a second pair of parallel sidewalls adjacent to the second dielectric material layer.

### Claim 9 (depends on 8)

The memory array structure of claim 8, wherein the first pair of parallel sidewalls are substantially orthogonal to the second pair of parallel sidewalls.