# US 11,444,208 B2 · Non-volatile memory device having low-k dielectric layer on sidewall of control gate electrode

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- Number: US 11,444,208 B2
- Document ID: US11444208B2
- Status: Granted
- Kind: B2
- Application number: 16/794,715
- Filed: 2020-02-19
- Published: 2020-08-27
- Granted: 2022-09-13
- Earliest claimed: 2019-02-21
- Assignees: Industry-University Cooperation Foundation Hanyang University
- Applicants: Industry-University Cooperation Foundation Hanyang University
- Inventors: Tae Whan Kim; Jun Gyu Lee; Hyun Soo Jung
- Web page: https://patentgrep.com/patent/US11444208B2

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits
- H10B 43/10: characterised by the top-view layout
- H10D 30/694: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A non-volatile memory device is provided. The non-volatile memory device comprises a semiconductor channel layer, a tunneling layer, a charge trap layer, and a blocking insulating layer arranged in sequence. A plurality of control gate electrodes are disposed on the blocking insulating layer. An inter-cell insulating layer is disposed between the control gate electrodes. A spacer insulating film is disposed between the control gate electrode and the inter-cell insulating layer, and the spacer insulating film has a lower dielectric constant than the inter-cell insulating layer. The charge trap layer extends under the plurality of control gate electrodes and is disposed under the inter-cell insulating layer and the spacer insulating film.

## Claims

### Claim 1

Non-volatile memory device comprising:
a semiconductor channel layer, a tunneling layer, a charge trap layer, and a blocking insulating layer arranged in sequence;
a plurality of control gate electrodes disposed on the blocking insulating layer;
an inter-cell insulating layer disposed between the control gate electrodes; and
a spacer insulating film disposed between the control gate electrode and the inter-cell insulating layer, the spacer insulating film having a lower dielectric constant than the inter-cell insulating layer,
wherein the charge trap layer extends under the plurality of control gate electrodes, and the charge trap layer is disposed under the inter-cell insulating layer and the spacer insulating film.

### Claim 2 (depends on 1)

The non-volatile memory device of claim 1, wherein the inter-cell insulating layer is a silicon oxide layer.

### Claim 3 (depends on 1)

The non-volatile memory device of claim 1, wherein the spacer insulating film is a silicon oxide-based low-k insulating film, an organic polymer film, or a silicone based polymeric layer.

### Claim 4 (depends on 3)

The non-volatile memory device of claim 3, wherein the silicon oxide-based low-k insulating film is a fluorine-doped silicon oxide layer, a carbon-doped silicon oxide layer, a porous silicon oxide layer, or a porous carbon-doped silicon oxide layer.

### Claim 5 (depends on 3)

The non-volatile memory device of claim 3, wherein the organic polymer film is polyimides, polynorbornenes, benzocyclobutene polymer, or PTFE (polytetrafluoroethylene).

### Claim 6 (depends on 3)

The non-volatile memory device of claim 3, wherein the silicone based polymeric layer is HSQ(hydrogen silsesquioxane) or MSQ(methyl silsesquioxane).

### Claim 7 (depends on 1)

The non-volatile memory device of claim 1, wherein the width of the spacer insulating film is smaller than the width of the inter-cell insulating layer.

### Claim 8 (depends on 1)

The non-volatile memory device of claim 1, wherein a ratio of a width of the spacer insulating film to a spacing between the control gate patterns is 0.05 to 0.2.

### Claim 9 (depends on 1)

The non-volatile memory device of claim 1, wherein a ratio of a width of the spacer insulating film to a spacing between the control gate patterns is 0.1 to 0.15.

### Claim 10 (depends on 1)

The non-volatile memory device of claim 1, wherein the spacer insulating film has a width of 2 to 8 nm.

### Claim 11 (depends on 1)

The non-volatile memory device of claim 1, wherein the spacer insulating film has a width of 4 to 6 nm.