# US 11,444,207 B2 · Lithium drifted thin film transistors for neuromorphic computing

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- Number: US 11,444,207 B2
- Document ID: US11444207B2
- Status: Granted
- Kind: B2
- Application number: 16/217,651
- Filed: 2018-12-12
- Published: 2020-06-18
- Granted: 2022-09-13
- Earliest claimed: 2018-12-12
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Babar Khan; Ning Li; Arvind Kumar; Yun Seog Lee; Joel P. de Souza; Devendra K. Sadana
- Web page: https://patentgrep.com/patent/US11444207B2

## CPC

- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/674: {characterised by the active materials}
- H10D 30/6745: {Polycrystalline or microcrystalline silicon}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/01348: {with substrate doping, e.g. N, Ge or C implantation, before formation of the insulator}
- H10D 64/01356: {the insulator being formed after the semiconductor body, the semiconductor being a Group IV material and not being silicon, e.g. Ge, SiGe or SiGeC (H10D64/01364, H10D64/01366 take precedence)}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/208: {of electrically inactive species}
- G06N 3/063: using electronic means
- G06N 3/065: Analogue means
- H10D 30/0312: {characterised by the gate electrodes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS

## Abstract

A semiconductor device includes a field-effect transistor, a first back-end-of-line (BEOL) metallization level and a second BEOL metallization level disposed above the first BEOL metallization level. A portion of the field-effect transistor includes lithium therein, and the field-effect transistor is integrated between the first and second BEOL metallization levels. The portion of the field-effect transistor including the lithium therein can be a channel layer, or a source and/or drain region.

## Claims

### Claim 1

A semiconductor device, comprising:
a field-effect transistor, wherein a portion of the field-effect transistor comprises lithium therein;
a first back-end-of-line metallization level; and
a second back-end-of-line metallization level disposed above the first back-end-of-line metallization level;
wherein the field-effect transistor is integrated between the first and second back-end-of-line metallization levels;
wherein the field-effect transistor comprises a channel layer, a source region, a drain region, a gate dielectric layer disposed on top surfaces of the channel layer, the source region and the drain region, and a gate disposed on a top surface of the gate dielectric layer;
wherein the source region and the drain region comprise the lithium therein;
wherein the lithium in the source region is at a higher concentration at an upper portion than at a lower portion of the source region;
wherein the lithium in the drain region is at a higher concentration at an upper portion than at a lower portion of the drain region; and
wherein the source region and the drain region are electrically connected to one or more contacts in the second back-end-of-line metallization level by respective vias located between the first and second back-end-of-line metallization levels and extending through the gate dielectric layer.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the channel layer further comprises one of amorphous silicon, polycrystalline silicon and poly-germanium.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a back gate;
wherein the field-effect transistor is disposed on the back gate.

### Claim 4 (depends on 3)

The semiconductor device according to claim 3, further comprising:
a dielectric layer disposed between the field-effect transistor and the back gate.

### Claim 5 (depends on 3)

The semiconductor device according to claim 3, wherein the back gate is disposed on a contact in the first back-end-of-line metallization level.

### Claim 6 (depends on 3)

The semiconductor device according to claim 3, wherein the back gate is electrically connected to a contact in the first back-end-of-line metallization level through a via.

### Claim 7

A semiconductor device, comprising:
an array of resistive processing unit devices, wherein each resistive processing unit device in the array comprises:
a field-effect transistor integrated between a first back-end-of-line metallization level and a second back-end-of-line metallization level above the first back-end-of-line metallization level;
wherein a portion of each field-effect transistor comprises lithium therein;
wherein each field-effect transistor comprises a channel layer, a source region, a drain region, and a gate dielectric layer disposed on top surfaces of the channel layer, the source region and the drain region;
wherein a gate of each field-effect transistor is electrically connected to a contact of the second back-end-of-line metallization level and is disposed on a top surface of the gate dielectric layer;
wherein the source region and the drain region comprise the lithium therein; and
wherein the lithium in the source region is at a higher concentration at an upper portion than at a lower portion of the source region;
wherein the lithium in the drain region is at a higher concentration at an upper portion than at a lower portion of the drain region; and
wherein the source region and the drain region are electrically connected to one or more contacts in the second back-end-of-line metallization level by respective vias located between the first and second back-end-of-line metallization levels and extending through the gate dielectric layer.

### Claim 8 (depends on 7)

The semiconductor device according to claim 7, wherein the channel layer further comprises one of amorphous silicon, polycrystalline silicon and poly-germanium.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1, wherein a depth of the lithium in each of the source and drain regions is less than a depth of the source and drain regions.

### Claim 10 (depends on 9)

The semiconductor device according to claim 9, wherein the depth of the source and drain regions is about 10 nm to about 100 nm.

### Claim 11 (depends on 1)

The semiconductor device according to claim 1, wherein each of the source and drain regions further comprises a dopant different from the lithium.

### Claim 12 (depends on 7)

The semiconductor device according to claim 7, wherein a depth of the lithium in each of the source and drain regions is less than a depth of the source and drain regions.

### Claim 13 (depends on 12)

The semiconductor device according to claim 12, wherein the depth of the source and drain regions is about 10 nm to about 100 nm.

### Claim 14 (depends on 7)

The semiconductor device according to claim 7, wherein each of the source and drain regions further comprises a dopant different from the lithium.