# US 11,444,205 B2 · Contact stacks to reduce hydrogen in thin film transistor

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- Number: US 11,444,205 B2
- Document ID: US11444205B2
- Status: Granted
- Kind: B2
- Application number: 16/143,001
- Filed: 2018-09-26
- Published: 2020-03-26
- Granted: 2022-09-13
- Earliest claimed: 2018-09-26
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Arnab Sen Gupta; Matthew Metz; Benjamin Chu-Kung; Abhishek Sharma; Van H. Le; Miriam R. Reshotko; Christopher J. Jezewski; Ryan Arch; Ande Kitamura; Jack T. Kavalieros; Seung Hoon Sung; Lawrence Wong; Tahir Ghani
- Web page: https://patentgrep.com/patent/US11444205B2

## CPC

- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)}
- H10D 62/402: {Amorphous materials}
- H10D 62/80: characterised by the materials
- H10D 64/01: Manufacture or treatment
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments herein describe techniques for a semiconductor device including a substrate and a transistor above the substrate. The transistor includes a channel layer above the substrate, a conductive contact stack above the substrate and in contact with the channel layer, and a gate electrode separated from the channel layer by a gate dielectric layer. The conductive contact stack may be a drain electrode or a source electrode. In detail, the conductive contact stack includes at least a metal layer, and at least a metal sealant layer to reduce hydrogen diffused into the channel layer through the conductive contact stack. Other embodiments may be described and/or claimed.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a transistor above the substrate, wherein the transistor includes:
a channel layer above the substrate;
a conductive contact stack above the substrate and in contact with the channel layer, wherein the conductive contact stack is a drain electrode or a source electrode, and the conductive contact stack includes at least a metal layer, and at least a metal sealant layer to reduce hydrogen diffused into the channel layer through the conductive contact stack, the metal selant layer over the metal layer; and
a gate electrode separated from the channel layer by a gate dielectric layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the metal sealant layer is in direct contact with the channel layer.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the metal sealant layer includes a material selected from the group consisting of TiN, AlTiN, AlTiOx, TaN, AlTaN, AlN, WOxNy, TiOxNy, SiOxNy, Al2O3, HfO2, TiO2, SiN, SiO2, SiCOH, Ta2O5, Y2O3, Ga2O3, ZrO2, HZO, YZO, HfTaOx, TaSiOx, HfSiOx, TaAlOx, HfAlOx, AlSiOx, AlSiNx, and HYO.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the metal sealant layer has a thickness in a range of about 1 Angstroms to 10 Angstroms.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the channel layer is above the gate electrode, and the conductive contact stack is above the channel layer.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the gate dielectric layer is above the channel layer, the gate electrode is above the gate dielectric layer, the conductive contact stack is above the channel layer, and the conductive contact stack is separated from the gate electrode by a spacer.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the conductive contact stack includes multiple metal sealant layers separated by one or more metal layers.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the metal sealant layer in the conductive contact stack includes multiple metal sealant sublayers.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the conductive contact stack includes at least a first metal layer and a second metal layer, the first metal layer includes TiN and the second metal layer includes W, Ru, or Si; or the first metal layer includes Ru and the second metal layer includes W or Si; or the first metal layer includes Si and the second metal layer W or TiN.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the conductive contact stack is a first conductive contact stack as the source electrode, and the transistor further includes:
a second conductive contact stack as the drain electrode, wherein the second conductive contact stack includes at least a metal layer, and at least a metal sealant layer to reduce hydrogen diffused into the channel layer through the second conductive contact stack; and
a passivation layer between the first conductive contact stack and the second conductive contact stack.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, further comprising:
the gate dielectric layer between the channel layer and the gate electrode, wherein the gate dielectric layer includes a material selected from the group consisting of silicon and oxygen; silicon and nitrogen; yttrium and oxygen; silicon, oxygen, and nitrogen; aluminum and oxygen; hafnium and oxygen; tantalum and oxygen; and titanium and oxygen.

### Claim 12 (depends on 1)

The semiconductor device of claim 1, wherein the channel layer includes a material selected from the group consisting of indium doped zinc oxide (IZO), zinc tin oxide (ZTO), amorphous silicon (a-Si), amorphous germanium (a-Ge), low-temperature polycrystalline silicon (LTPS), transition metal dichalcogenide (TMD), yttrium-doped zinc oxide (YZO), polysilicon, poly germanium doped with boron, poly germanium doped with aluminum, poly germanium doped with phosphorous, poly germanium doped with arsenic, indium oxide, tin oxide, zinc oxide, gallium oxide, indium gallium zinc oxide (IGZO), copper oxide, nickel oxide, cobalt oxide, indium tin oxide, tungsten disulphide, molybdenum disulphide, molybdenum selenide, black phosphorus, indium antimonide, graphene, graphyne, borophene, germanene, silicene, Si2BN, stanene, phosphorene, molybdenite, poly-III-V like InAs, InGaAs, InP, amorphous InGaZnO (a-IGZO), crystal-like InGaZnO (c-IGZO), GaZnON, ZnON, or C-Axis Aligned Crystal (CAAC), molybdenum and sulfur, and a group-VI transition metal dichalcogenide.

### Claim 13 (depends on 1)

The semiconductor device of claim 1, wherein the gate electrode or the metal layer of the conductive contact stack includes a material selected from the group consisting of titanium (Ti), molybdenum (Mo), gold (Au), platinum (Pt), aluminum (Al), nickel (Ni), copper (Cu), chromium (Cr), hafnium (Hf), indium (In), and an alloy of Ti, Mo, Au, Pt, Al, Ni, Cu, Cr, TiAlN, HfAlN, or InAlO.

### Claim 14 (depends on 1)

The semiconductor device of claim 1, wherein the substrate includes a silicon substrate, a glass substrate, a metal substrate, or a plastic substrate.

### Claim 15 (depends on 1)

The semiconductor device of claim 1, wherein the transistor is within an interconnect structure that is above the substrate.

### Claim 16

A method for forming a thin film transistor (TFT), the method comprising:
forming a channel layer above a substrate;
forming a conductive contact stack above the substrate and in contact with the channel layer, wherein the conductive contact stack is a drain electrode or a source electrode, and the conductive contact stack includes at least a metal layer, and at least a metal sealant layer to reduce hydrogen diffused into the channel layer through the conductive contact stack, the metal selant layer over the metal layer; and
forming a gate electrode separated from the channel layer by a gate dielectric layer.

### Claim 17 (depends on 16)

The method of claim 16, wherein the metal sealant layer includes a material selected from the group consisting of TiN, AlTiN, AlTiOx, TaN, AlTaN, AlN, WOxNy, TiOxNy, SiOxNy, Al2O3, HfO2, TiO2, SiN, SiO2, SiCOH, Ta2O5, Y2O3, Ga2O3, ZrO2, HZO, YZO, HfTaOx, TaSiOx, HfSiOx, TaAlOx, HfAlOx, AlSiOx, AlSiNx, and HYO.

### Claim 18 (depends on 16)

The method of claim 16, wherein the conductive contact stack is a first conductive contact stack as the source electrode, and the method further includes:
forming a second conductive contact stack as the drain electrode, wherein the second conductive contact stack includes at least a metal layer, and at least a metal sealant layer to reduce hydrogen diffused into the channel layer through the second conductive contact stack; and
forming a passivation layer between the first conductive contact stack and the second conductive contact stack.

### Claim 19 (depends on 16)

The method of claim 16, wherein the channel layer is above the gate electrode, and the conductive contact stack is above the channel layer.

### Claim 20 (depends on 16)

The method of claim 16, wherein the gate dielectric layer is above the channel layer, the gate electrode is above the gate dielectric layer, the conductive contact stack is above the channel layer, and the conductive contact stack is separated from the gate electrode by a spacer.

### Claim 21 (depends on 16)

The method of claim 16, wherein the conductive contact stack includes multiple metal sealant layers separated by one or more metal layers.

### Claim 22

A semiconductor device, comprising:
a substrate;
a transistor above the substrate, wherein the transistor includes:
a channel layer above the substrate;
a conductive contact stack above the substrate and in contact with the channel layer, wherein the conductive contact stack is a drain electrode or a source electrode, and the conductive contact stack includes at least a metal layer, and at least a metal sealant layer to reduce hydrogen diffused into the channel layer through the conductive contact stack, wherein the conductive contact stack includes multiple metal sealant layers separated by one or more metal layers; and
a gate electrode separated from the channel layer by a gate dielectric layer.

### Claim 23

A semiconductor device, comprising:
a substrate;
a transistor above the substrate, wherein the transistor includes:
a channel layer above the substrate;
a conductive contact stack above the substrate and in contact with the channel layer, wherein the conductive contact stack is a drain electrode or a source electrode, and the conductive contact stack includes at least a metal layer, and at least a metal sealant layer to reduce hydrogen diffused into the channel layer through the conductive contact stack, wherein the conductive contact stack includes at least a first metal layer and a second metal layer, the first metal layer includes TiN and the second metal layer includes W, Ru, or Si; or the first metal layer includes Ru and the second metal layer includes W or Si; or the first metal layer includes Si and the second metal layer W or TiN; and
a gate electrode separated from the channel layer by a gate dielectric layer.