# US 11,444,204 B2 · Transistor device with channel recess structure and method of providing same

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- Number: US 11,444,204 B2
- Document ID: US11444204B2
- Status: Granted
- Kind: B2
- Application number: 15/939,081
- Filed: 2018-03-28
- Published: 2019-10-03
- Granted: 2022-09-13
- Earliest claimed: 2018-03-28
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Abhishek A. Sharma; Van H. Le; Sean T. Ma; Jack Kavalieros; Benjamin Chu-Kung
- Web page: https://patentgrep.com/patent/US11444204B2

## CPC

- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/6706: {for preventing leakage current (TFTs characterised by the properties of the source or drain H10D30/6713)}
- H10D 30/6728: {Vertical TFTs}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Techniques and mechanisms for improved performance characteristics of a transistor device. In an embodiment, a transistor of an integrated circuit comprises a source, a drain, a gate, a gate dielectric and a semiconductor structure which adjoins the gate dielectric. The semiconductor structure is configured to provide a conductive channel between the source and drain. The semiconductor structure includes first, second and third portions, the second portion between the source and the gate, and the third portion between the drain and the gate, wherein the first portion connects the second portion and third portion to one another. A thickness of the first portion is less than another thickness of one of the second portion or the third portion. In another embodiment, the locations of thicker portions of semiconductor structure mitigate overall transistor capacitance, while a thinner intermediary portion of the semiconductor structure promotes good sub-threshold swing characteristics.

## Claims

### Claim 1

A method comprising:
forming a gate of a single-gate transistor, the gate comprising a metal;
forming a layer adjacent to the gate, the layer comprising a dielectric material;
forming a semiconductor structure adjacent to the layer, the semiconductor structure comprising:
a first body of a first semiconductor material, wherein the first semiconductor material is doped with a first dopant, wherein the layer extends between the first body and the gate, and wherein the first body forms at least in part a recess of the semiconductor structure, wherein a bottom of the recess is formed with a surface of the first body;
a second body of a second semiconductor material other than the first semiconductor material, wherein the second semiconductor material is doped with a second dopant, wherein the first body extends between the second body and the layer; and
a third body of the second semiconductor material, wherein the first body extends between the third body and the layer;
forming a source of the single-gate transistor, wherein the second body of the semiconductor structure is between the source and the first body;
forming a drain of the single-gate transistor, wherein the third body of the semiconductor structure is between the drain and the first body; and
forming an insulator structure which, at the bottom of the recess, and at a top of the recess, extends horizontally across the recess to each of the second body and the third body;
wherein:
forming the semiconductor structure comprises:
forming a first patterned mask, wherein a first hole and a second hole each extend through the first patterned mask;
performing a first deposition into each of the first hole and the second hole;
forming a second patterned mask, wherein a third hole extends through the second patterned mask; and
performing a second deposition through the third hole, wherein a semiconductor body formed by the second deposition connects semiconductor bodies formed by the first deposition;
a thickness of the first body is substantially the same in each of a first region under the second body, a second region under the third body, and a third region under the recess; and
the thickness of the first body is less than 80% of a maximum height of one of the second body or the third body above the layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein a difference between a first thickness of one of the second body or the third body and a second thickness of the first body is at least 1.0 nanometers.

### Claim 3 (depends on 1)

The method of claim 1, wherein the insulator structure fills the recess.

### Claim 4 (depends on 3)

The method of claim 3, wherein the insulator structure extends from the recess to fill any region between the source and the drain.