# US 11,444,202 B2 · Semiconductor device and method of forming the same

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- Number: US 11,444,202 B2
- Document ID: US11444202B2
- Status: Granted
- Kind: B2
- Application number: 16/745,340
- Filed: 2020-01-17
- Published: 2021-07-22
- Granted: 2022-09-13
- Earliest claimed: 2020-01-17
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Bo-Feng Young; Sai-Hooi Yeong; Chi-On Chui; Chien-Ning Yao
- Web page: https://patentgrep.com/patent/US11444202B2

## CPC

- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/0197: {the inner spacers having different properties}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/508: {characterised by the relative sizes, shapes or dispositions of the inner spacers}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3462: {Nanowires}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Provided are a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a plurality of semiconductor nanosheets, a source/drain (S/D) region, a gate stack, and a liner layer. The substrate includes at least one fin. The plurality of semiconductor nanosheets are stacked on the at least one fin. The S/D region abuts the plurality of semiconductor nanosheets. The gate stack wraps the plurality of semiconductor nanosheets. The liner layer lines a bottom surface and a sidewall of the S/D region and is sandwiched between the S/D region and the gate stack.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate comprising at least one fin;
a plurality of semiconductor nanosheets stacked on the at least one fin;
a source/drain (S/D) region abutting the plurality of semiconductor nanosheets;
a gate stack wrapping the plurality of semiconductor nanosheets;
an inner spacer sandwiched between the S/D region and the gate stack to electrically isolate the S/D region from the gate stack, wherein the inner spacer has an outer sidewall concave from a sidewall of the plurality of semiconductor nanosheets to form a plurality of cavities between the plurality of semiconductor nanosheets; and
a liner layer lining a bottom surface and a sidewall of the S/D region and sandwiched between the S/D region and the inner spacer, wherein the liner layer continuously vertically extends between adjacent semiconductor nanosheets to conformally fill in the plurality of cavities and completely cover the outer sidewall of the inner spacer, wherein the S/D region has a plurality of protrusions respectively filling into the plurality of cavities, and the plurality of protrusions are vertically sandwiched between the plurality of semiconductor nanosheets.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the liner layer is a polysilicon layer, a germanium (Ge) layer, a silicon-germanium (SiGe) layer, or a combination thereof.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the liner layer extends between the S/D region and the plurality of semiconductor nanosheets to separate the S/D region from the plurality of semiconductor nanosheets.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein a material of the S/D region is derived from or epitaxial grown from a material of the liner layer.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein lateral distances from the sidewalls of the plurality of semiconductor nanosheets to the outer sidewalls of the plurality of inner spacers gradually increase along a direction from the substrate to the gate stack.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the gate stack comprises a gate dielectric layer and a gate electrode on the gate dielectric layer, the gate dielectric layer wraps the plurality of semiconductor nanosheets, and a portion of the gate electrode is sandwiched between two adjacent semiconductor nanosheets, wherein the liner layer further covers a sidewall of the portion of the gate electrode between the two adjacent semiconductor nanosheets.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the gate stack comprises a gate dielectric layer and a gate electrode on the gate dielectric layer, and portions of the gate dielectric layer wrapping the plurality of semiconductor nanosheets are connected together to form a continuous region.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, further comprising a spacer covering a sidewall of the gate stack on the plurality of semiconductor nanosheets, wherein the liner layer further extends to directly contact a sidewall of the spacer, so that the spacer is sandwiched between the liner layer and the gate stack on the plurality of semiconductor nanosheets.

### Claim 9

A method of forming a semiconductor device, comprising:
forming a semiconductor stack on a substrate, wherein the semiconductor stack comprises a plurality of first layers and a plurality of second layers stacked alternately;
patterning the semiconductor stack and the substrate to form a plurality of trenches in the substrate and a stack of semiconductor strips between the plurality of trenches;
forming a dummy gate stack across the at least one stack of semiconductor strips;
removing a portion of the stack of semiconductor strips at opposite sides of the dummy gate stack to form source/drain (S/D) recesses exposing the substrate;
laterally recessing the plurality of first layers to form a plurality of cavities;
forming a plurality of inner spacers in the plurality of cavities respectively after laterally recessing the plurality of first layers;
forming a liner layer to cover the S/D recesses and the plurality of cavities, wherein the liner layer continuously vertically extends between adjacent second layers to conformally fill in the plurality of cavities and completely cover outer sidewalls of the plurality of inner spacers; and
epitaxially growing S/D regions from the liner layer, wherein the S/D regions have a plurality of protrusions respectively filling into the plurality of cavities, and the plurality of protrusions are vertically sandwiched between the plurality of second layers.

### Claim 10 (depends on 9)

The method of claim 9, wherein the S/D regions is formed to fill up the S/D recesses.

### Claim 11 (depends on 9)

The method of claim 9, wherein depths of the plurality of cavities gradually increase along a direction from the substrate to the dummy gate stack.

### Claim 12 (depends on 9)

The method of claim 9, further comprising:
removing the dummy gate stack;
performing an etching process to remove the plurality of first layers and form a plurality of gaps between the plurality of the second layers;
forming a gate dielectric layer wrapping the plurality of the second layers; and
forming a gate electrode to cover the gate dielectric layer.

### Claim 13 (depends on 12)

The method of claim 12, wherein the plurality of first layers and the plurality of second layers have different etching selectivities in the etching process.

### Claim 14 (depends on 9)

The method of claim 9, wherein the outer sidewalls of the plurality of inner spacers are concave from sidewalls of the plurality of second layers.

### Claim 15

A semiconductor device, comprising:
a substrate comprising at least one fin;
a plurality of semiconductor nanosheets stacked on the at least one fin;
a source/drain (S/D) region abutting the plurality of semiconductor nanosheets;
a gate stack wrapping the plurality of semiconductor nanosheets, wherein the gate stack comprises a gate dielectric layer and a gate electrode on the gate dielectric layer, wherein the gate dielectric layer between the plurality of semiconductor nanosheets has an outer sidewall concave from a sidewall of the plurality of semiconductor nanosheet to form a plurality of cavities between the plurality of semiconductor nanosheets; and
a liner layer lining a bottom surface and a sidewall of the S/D region and sandwiched between the S/D region and the gate stack, wherein the liner layer continuously vertically extends between adjacent semiconductor nanosheets to conformally fill in the plurality of cavities and completely cover the outer sidewall of the gate dielectric layer, wherein the liner layer is in direct contact with the gate dielectric layer between the plurality of semiconductor nanosheets.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the liner layer is a polysilicon layer, a germanium (Ge) layer, a silicon-germanium (SiGe) layer, or a combination thereof.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein a first portion of the liner layer sandwiched between the S/D region and the gate stack has a first thickness, a second portion of the liner layer sandwiched between the S/D region and the plurality of semiconductor nanosheets has a second thickness, and the first thickness is greater than the second thickness.

### Claim 18 (depends on 15)

The semiconductor device of claim 15, wherein a material of the S/D region is derived from or epitaxial grown from a material of the liner layer.

### Claim 19 (depends on 15)

The semiconductor device of claim 15, wherein a lateral distance from the sidewall of the plurality of semiconductor nanosheets to the outer sidewall of the plurality of inner spacers gradually increases along a direction from the substrate to the gate stack.

### Claim 20 (depends on 15)

The semiconductor device of claim 15, further comprising a spacer covering a sidewall of the gate stack on the plurality of semiconductor nanosheets, wherein the liner layer further extends to directly contact a sidewall of the spacer, so that the spacer is sandwiched between the liner layer and the gate stack on the plurality of semiconductor nanosheets.