# US 11,444,201 B2 · Leakage current reduction in polysilicon-on-active-edge structures

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- Number: US 11,444,201 B2
- Document ID: US11444201B2
- Status: Granted
- Kind: B2
- Application number: 16/831,010
- Filed: 2020-03-26
- Published: 2021-09-30
- Granted: 2022-09-13
- Earliest claimed: 2020-03-26
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Youn Sung Choi; Kwanyong Lim; Youseok Suh; Hyunwoo Park
- Web page: https://patentgrep.com/patent/US11444201B2

## CPC

- H10D 30/6215: {having multiple independently-addressable gate electrodes}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0142: {the gate conductors having different shapes or dimensions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 84/014: {the gate conductors having different materials or different implants}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Certain aspects of the present disclosure generally relate to techniques for reducing leakage current in polysilicon-on-active-edge structures. An example transistor structure includes one or more active devices and at least one dummy device disposed at an edge of the transistor structure, wherein the at least one dummy device has a different gate structure than the one or more active devices.

## Claims

### Claim 1

A transistor structure comprising:
one or more active devices; and
at least one dummy device disposed at an edge of the transistor structure, wherein the at least one dummy device has a different gate structure than the one or more active devices, wherein:
a first gate structure of the at least one dummy device comprises a positive work function metal layer and a negative work function metal layer; and
a second gate structure of the one or more active devices comprises a negative work function metal layer and lacks a positive work function metal layer.

### Claim 2 (depends on 1)

The transistor structure of claim 1, wherein the at least one dummy device comprises a polysilicon on oxide-defined (OD) edge (PODE) structure.

### Claim 3 (depends on 1)

The transistor structure of claim 1, wherein a first gate structure of the at least one dummy device has a smaller width than a second gate structure of one of the active devices.

### Claim 4 (depends on 3)

The transistor structure of claim 3, wherein:
the first gate structure of the at least one dummy device has a first gate width that is greater than a first channel length disposed underneath the first gate structure of the at least one dummy device; and
the second gate structure of the one of the active devices has a second gate width that is the same as a second channel length disposed underneath the second gate structure of the one of the active devices.

### Claim 5 (depends on 1)

The transistor structure of claim 1, wherein:
a first gate structure of the at least one dummy device has a first gate width that is greater than a first channel length disposed underneath the first gate structure of the at least one dummy device; and
a second gate structure of one of the active devices has a second gate width that is the same as a second channel length disposed underneath the second gate structure of the one of the active devices.

### Claim 6 (depends on 1)

The transistor structure of claim 1, wherein a first gate structure of the at least one dummy device has a greater width than a second gate structure of one of the active devices.

### Claim 7 (depends on 6)

The transistor structure of claim 6, wherein:
the first gate structure of the at least one dummy device has a first gate width that is greater than a first channel length disposed underneath the first gate structure of the at least one dummy device; and
the second gate structure of the one of the active devices has a second gate width that is the same as a second channel length disposed underneath the second gate structure of the one of the active devices.

### Claim 8 (depends on 6)

The transistor structure of claim 6, wherein an active area disposed underneath the first gate structure comprises a first portion having a first width and a second portion having a second width that is less than the first width.

### Claim 9 (depends on 8)

The transistor structure of claim 8, wherein a length of the first portion of the active area disposed underneath the first gate structure is less than a length of the second portion of the active area disposed underneath the first gate structure.

### Claim 10 (depends on 1)

The transistor structure of claim 1, wherein a gate structure of the at least one dummy device overhangs and extends beyond three consecutive edges of an active area.

### Claim 11 (depends on 1)

The transistor structure of claim 1, wherein an active area disposed underneath a gate structure of the at least one dummy device comprises a first portion having a first width and a second portion having a second width that is less than the first width.

### Claim 12 (depends on 11)

The transistor structure of claim 11, wherein a length of the first portion of the active area disposed underneath the gate structure of the at least one dummy device is greater than a length of the second portion of the active area disposed underneath the gate structure of the at least one dummy device.

### Claim 13 (depends on 1)

The transistor structure of claim 1, further comprising:
a plurality of parallel channel structures;
one or more gate conductors, each gate conductor being disposed at least above the plurality of parallel channel structures and having a longitudinal axis disposed perpendicular to the plurality of parallel channel structures, wherein intersections of the one or more gate conductors and the plurality of parallel channel structures form the one or more active devices; and
at least one dummy structure disposed at the edge of the transistor structure, disposed at least above the plurality of parallel channel structures, and having a longitudinal axis disposed perpendicular to the plurality of parallel channel structures, wherein intersections of the at least one dummy structure and the plurality of parallel channel structures form the at least one dummy device.

### Claim 14 (depends on 13)

The transistor structure of claim 13, wherein the plurality of parallel channel structures comprise a plurality of parallel fins and wherein the one or more active devices comprise one or more fin field-effect transistors (finFETs).

### Claim 15 (depends on 13)

The transistor structure of claim 13, wherein the plurality of parallel channel structures define an oxide-defined (OD) area and wherein the at least one dummy device comprises a polysilicon on OD edge (PODE) structure.

### Claim 16 (depends on 1)

The transistor structure of claim 1, wherein:
the at least one dummy device is configured to have no active function; and
the at least one dummy device comprises a first gate structure that includes one or more different layers compared to a second gate structure of the one or more active devices.

### Claim 17

A method for fabricating a transistor structure, comprising:
forming one or more active devices; and
forming at least one dummy device disposed at an edge of the transistor structure, wherein the at least one dummy device has a different gate structure than the one or more active devices, wherein:
a first gate structure of the at least one dummy device comprises a positive work function metal layer and a negative work function metal layer; and
a second gate structure of the one or more active devices comprises a negative work function metal layer and lacks a positive work function metal layer.

### Claim 18 (depends on 17)

The method of claim 17, wherein:
a first gate structure of the at least one dummy device has a smaller width than a second gate structure of one of the active devices;
the first gate structure of the at least one dummy device has a first gate width that is greater than a first channel length disposed underneath the first gate structure of the at least one dummy device; and
the second gate structure of one of the active devices has a second gate width that is the same as a second channel length disposed underneath the second gate structure of the one of the active devices.