# US 11,444,200 B2 · Semiconductor structure with isolating feature and method for forming the same

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- Number: US 11,444,200 B2
- Document ID: US11444200B2
- Status: Granted
- Kind: B2
- Application number: 17/082,711
- Filed: 2020-10-28
- Published: 2021-07-01
- Granted: 2022-09-13
- Earliest claimed: 2019-12-26
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Yu-Xuan Huang; Ching-Wei Tsai; Hou-Yu Chen; Kuan-Lun Cheng
- Web page: https://patentgrep.com/patent/US11444200B2

## CPC

- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 62/119: {Nanowire, nanosheet or nanotube semiconductor bodies}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/364: {of IGFETs}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and a fin structure protruding from the substrate. The semiconductor structure also includes nanostructures formed over the fin structure and a gate structure surrounding the nanostructures. The semiconductor structure also includes a source/drain structure connected to the nanostructures and an isolating feature sandwiched between the fin structure and the source/drain structure.

## Claims

### Claim 1

A semiconductor structure, comprising:
a substrate;
a fin structure protruding from the substrate;
nanostructures formed over the fin structure;
inner spacers vertically sandwiched between the nanostructures;
a gate structure surrounding the nanostructures;
a source/drain structure connected to the nanostructures; and
an isolating feature sandwiched between the fin structure and the source/drain structure,
wherein a portion of the inner spacers is laterally sandwiched between the isolating feature and the gate structure.

### Claim 2 (depends on 1)

The semiconductor structure as claimed in claim 1, wherein a top surface of the isolating feature is lower than a bottommost surface of the nanostructures.

### Claim 3 (depends on 1)

The semiconductor structure as claimed in claim 1, wherein a top surface of the isolating feature is higher than a bottommost surface of the nanostructures.

### Claim 4 (depends on 1)

The semiconductor structure as claimed in claim 1, wherein the isolating feature is made of an undoped semiconductor material.

### Claim 5 (depends on 1)

The semiconductor structure as claimed in claim 1, wherein the isolating feature is made of an insulating material.

### Claim 6 (depends on 1)

The semiconductor structure as claimed in claim 1, wherein the isolating feature has a curved top surface.

### Claim 7 (depends on 1)

The semiconductor structure as claimed in claim 1, wherein the isolating feature comprises a liner in direct contact with the fin structure and an insulating material layer over the liner and in direct contact with the source/drain structure.

### Claim 8 (depends on 1)

The semiconductor structure as claimed in claim 1, further comprising:
a gate spacer formed on a sidewall of the gate structure, wherein the gate spacer vertically overlaps the inner spacers.

### Claim 9 (depends on 1)

The semiconductor structure as claimed in claim 1, wherein a top surface of the isolating feature is higher than a bottom surface of the inner spacers.

### Claim 10

A semiconductor structure, comprising:
a substrate;
a first fin structure protruding from the substrate;
first nanostructures formed over the first fin structure;
a gate structure wrapping around the first nanostructures at a channel region;
an isolating feature covering a top surface of the first fin structure at a source/drain region; and
a first source/drain structure formed over the isolating feature and connected to the first nanostructures,
wherein the isolating feature is separated from the first nanostructures by the first source/drain structure.

### Claim 11 (depends on 10)

The semiconductor structure as claimed in claim 10, further comprising:
first inner spacers formed between the first nanostructures,
wherein the isolating feature and the gate structure are separated by the first inner spacers.

### Claim 12 (depends on 10)

The semiconductor structure as claimed in claim 10, further comprising:
an isolation structure formed around the first fin structure, wherein a bottom surface of the isolating feature is lower than a top surface of the isolation structure.

### Claim 13 (depends on 10)

The semiconductor structure as claimed in claim 10, wherein the isolating feature is spaced apart from the gate structure.

### Claim 14

A method for manufacturing a semiconductor structure, comprising:
alternately stacking first semiconductor material layers and second semiconductor material layers over a substrate;
patterning the first semiconductor material layers, the second semiconductor material layers, and the substrate to form a fin structure;
forming spacers at opposite sides of the fin structure;
forming a source/drain recess in a source/drain region of the fin structure between the spacers;
forming an isolating feature in the source/drain recess between the spacers;
forming a source/drain structure covering the isolating feature;
removing the first semiconductor material layers to form nanostructures from the second semiconductor material layers in a channel region; and
forming a gate structure wrapping around the nanostructures.

### Claim 15 (depends on 14)

The method for manufacturing the semiconductor structure as claimed in claim 14, wherein a middle portion of the isolating feature is higher than an edge portion of the isolating feature.

### Claim 16 (depends on 14)

The method for manufacturing the semiconductor structure as claimed in claim 14, wherein a middle portion of the isolating feature is lower than an edge portion of the isolating feature.

### Claim 17 (depends on 14)

The method for manufacturing the semiconductor structure as claimed in claim 14, further comprising:
removing the first semiconductor material layers and the second semiconductor material layers at the source/drain region to form the source/drain recess,
wherein the isolating feature is formed in a bottom portion of the source/drain recess.

### Claim 18 (depends on 14)

The method for manufacturing the semiconductor structure as claimed in claim 14, wherein the isolating feature is made of an undoped Si or undoped SiGe.

### Claim 19 (depends on 14)

The method for manufacturing the semiconductor structure as claimed in claim 14, wherein the isolating feature comprises multiple dielectric layers.

### Claim 20 (depends on 14)

The method for manufacturing the semiconductor structure as claimed in claim 14, further comprising:
forming an isolation structure around the fin structure,
wherein a top portion of the isolating feature is higher than a top surface of the isolating feature, and a bottom portion of the isolating feature is lower than a bottom surface of the isolation structure.