# US 11,444,199 B2 · Method of manufacturing a semiconductor device and a semiconductor device

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- Number: US 11,444,199 B2
- Document ID: US11444199B2
- Status: Granted
- Kind: B2
- Application number: 16/984,075
- Filed: 2020-08-03
- Published: 2022-02-03
- Granted: 2022-09-13
- Earliest claimed: 2020-08-03
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Shahaji B. More; Shih-Chieh Chang; Cheng-Han Lee; Pei-Shan Lee
- Web page: https://patentgrep.com/patent/US11444199B2

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 84/0167: {Manufacturing their channels}
- H10D 30/0195: {forming inner spacers between adjacent channels, e.g. changing their shapes or sizes}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/508: {characterised by the relative sizes, shapes or dispositions of the inner spacers}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6748: {having a multilayer structure or superlattice structure}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions}
- H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device includes semiconductor wires or sheets disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires or sheets, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires or sheets, a gate electrode layer disposed on the gate dielectric layer and wrapping around each channel region, and insulating spacers disposed in spaces, respectively. The spaces are defined by adjacent semiconductor wires or sheets, the gate electrode layer and the source/drain region. The source/drain epitaxial layer includes multiple doped SiGe layers having different Ge contents and at least one of the source/drain epitaxial layers is non-doped SiGe or Si.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, comprising:
forming an upper fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked over a lower fin structure;
forming a sacrificial gate structure over the upper fin structure;
etching a source/drain region of the upper fin structure, which is not covered by the sacrificial gate structure, thereby forming a source/drain space;
laterally etching the first semiconductor layers through the source/drain space; forming an inner spacer made of a dielectric material on an end of each of the etched first semiconductor layers; and
forming a source/drain epitaxial layer in the source/drain space to cover the inner spacer,
wherein in etching the source/drain region, a part of the lower fin structure is also etched to form a recess,
the source/drain epitaxial layer includes multiple SiGe layers having different Ge contents,
the multiple SiGe layers comprise:
a first SiGe layer;
a second SiGe layer having a higher Ge content than the first SiGe layer disposed over the first SiGe layer; and
a third SiGe layer having a higher Ge content than the second SiGe layer disposed over the second SiGe layer,
a Ge content of the third SiGe layer (50-3) increases as growth of the third SiGe layer, and
a Ge content of the second SiGe layer is constant.

### Claim 2 (depends on 1)

The method of claim 1,
wherein a Ge content of the first SiGe layer increases as growth of the first SiGe layer.

### Claim 3 (depends on 1)

The method of claim 1,
wherein the source/drain epitaxial layer further includes a fourth SiGe layer over the third SiGe layer.

### Claim 4 (depends on 3)

The method of claim 3,
wherein a Ge content of the fourth SiGe layer decreases as growth of the fourth SiGe layer.

### Claim 5 (depends on 3)

The method of claim 3, wherein the fourth SiGe layer is in contact with the first, second and third SiGe layers.

### Claim 6 (depends on 3)

The method of claim 3, wherein a bottom of the fourth SiGe layer is located above an uppermost one of the second semiconductor layers.

### Claim 7 (depends on 3)

The method of claim 3, wherein the source/drain epitaxial layer further includes a fifth epitaxial layer below the first SiGe layer.

### Claim 8 (depends on 7)

The method of claim 7,
wherein the fifth epitaxial layer is in contact with ends of the second semiconductor layers and the inner spacer, and the first SiGe layer is formed on the fifth epitaxial layer.

### Claim 9 (depends on 7)

The method of claim 7, wherein the fifth epitaxial layer is non-doped silicon.

### Claim 10 (depends on 1)

The method of claim 1, wherein a (111) surface is exposed in the recess.

### Claim 11 (depends on 10)

The method of claim 10, wherein an end of each of the second semiconductor layers is an (110) surface.

### Claim 12

A method of manufacturing a semiconductor device, comprising:
forming an upper fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked over a lower fin structure;
forming a sacrificial gate structure over the upper fin structure;
etching a source/drain region of the upper fin structure, which is not covered by the sacrificial gate structure, thereby forming a source/drain space;
laterally etching the first semiconductor layers through the source/drain space;
forming an inner spacer made of a dielectric material on an end of each of the etched first semiconductor layers; and
forming a source/drain epitaxial layer in the source/drain space to cover the inner spacer, wherein:
in etching the source/drain region, a part of the lower fin structure is also etched to form a recess,
the source/drain epitaxial layer includes multiple SiGe layers having different Ge contents,
the multiple SiGe layers comprise:
a first SiGe layer;
a second SiGe layer having a higher Ge content than the first SiGe layer disposed over the first SiGe layer; and
a third SiGe layer having a higher Ge content than the second SiGe layer disposed over the second SiGe layer,
a Ge content of the third SiGe layer increases as growth of the third SiGe layer, and
a Ge content of the second SiGe layer is constant, and
the recess has a V-shape or a triangular shape in cross section.

### Claim 13 (depends on 12)

The method of claim 12, wherein the first SiGe layer includes B, and a B concentration of the first SiGe layer increases as the first SiGe layer is grown.

### Claim 14 (depends on 13)

The method of claim 13, wherein the second SiGe layer includes B, and a B concentration of the second SiGe layer is constant.

### Claim 15 (depends on 14)

The method of claim 14, wherein the B concentration of the second SiGe layer is higher than the B concentration of the first SiGe layer.

### Claim 16 (depends on 15)

The method of claim 15, wherein the third SiGe layer includes B, and a B concentration of the third SiGe layer is higher than the B concentration of the second SiGe layer.

### Claim 17 (depends on 12)

The method of claim 12, wherein the recess is fully filled by non-doped Si or non-doped SiGe.

### Claim 18

A method of manufacturing a semiconductor device, comprising:
forming an upper fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked over a lower fin structure;
forming a sacrificial gate structure over the upper fin structure;
etching a source/drain region of the upper fin structure, which is not covered by the sacrificial gate structure, thereby forming a source/drain space;
laterally etching the first semiconductor layers through the source/drain space;
forming an inner spacer made of a dielectric material on an end of each of the etched first semiconductor layers; and
forming a source/drain epitaxial layer in the source/drain space to cover the inner spacer, wherein:
in etching the source/drain region, a part of the lower fin structure is also etched to form a recess,
the source/drain epitaxial layer includes multiple SiGe layers having different Ge contents,
the multiple SiGe layers comprise:
a first SiGe layer;
a second SiGe layer having a higher Ge content than the first SiGe layer disposed over the first SiGe layer; and
a third SiGe layer having a higher Ge content than the second SiGe layer disposed over the second SiGe layer,
a Ge content of the third SiGe layer increases as growth of the third SiGe layer, and
a Ge content of the second SiGe layer is constant, and
a thickness in a horizontal direction of the first SiGe layer on ends of the second semiconductor layers is greater than a thickness in the horizontal direction of the first SiGe layer on the inner spacer.

### Claim 19 (depends on 18)

The method of claim 18, wherein:
a non-doped Si or SiGe layer is formed before the first SiGe layer is formed, and
between forming the non-doped Si or SiGe layer and forming the first SiGe layer, an annealing operation is performed in an ambient containing hydrogen at a higher temperature than temperatures for forming the non-doped Si or SiGe layer and forming the first SiGe layer.

### Claim 20 (depends on 19)

The method of claim 19,
wherein before forming the non-doped Si or SiGe layer, a chemical treatment using an HCI gas is performed.