# US 11,444,198 B2 · Work function control in gate structures

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,444,198 B2
- Document ID: US11444198B2
- Status: Granted
- Kind: B2
- Application number: 16/887,203
- Filed: 2020-05-29
- Published: 2021-12-02
- Granted: 2022-09-13
- Earliest claimed: 2020-05-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Hsin-Yi Lee; Cheng-Lung Hung; Ji-Cheng Chen; Weng Chang; Chi On Chui
- Web page: https://patentgrep.com/patent/US11444198B2

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 84/0177: {the gate conductors having different materials or different implants}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The semiconductor device includes a fin structure disposed on a substrate, a nanostructured channel region disposed on the fin structure, and a gate-all-around (GAA) structure surrounding the nanostructured channel region. The GAA structure includes a high-K (HK) gate dielectric layer with a metal doped region having dopants of a first metallic material, a p-type work function metal (pWFM) layer disposed on the HK gate dielectric layer, a bimetallic nitride layer interposed between the HK gate dielectric layer and the pWFM layer, an n-type work function metal (nWFM) layer disposed on the pWFM layer, and a gate metal fill layer disposed on the nWFM layer. The pWFM layer includes a second metallic material and the bimetallic nitride layer includes the first and second metallic materials.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a fin structure disposed on the substrate;
a nanostructured channel region disposed on the fin structure; and
a gate-all-around (GAA) structure surrounding the nanostructured channel region, wherein the GAA structure comprises:
a high-K (HK) gate dielectric layer with a metal doped region having dopants of a first metallic material;
a first work function metal (WFM) layer disposed on the HK gate dielectric layer, wherein the first WFM layer includes a second metallic material;
a bimetallic nitride layer interposed between the HK gate dielectric layer and the first WFM layer, wherein the bimetallic nitride layer comprises the first and second metallic materials;
a second WFM layer disposed on the first WFM layer; and
a gate metal fill layer disposed on the second WFM layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a concentration of the first metallic material in the metal doped region is greater than a concentration of the first metallic material in the bimetallic nitride layer.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein a concentration of the second metallic material in the first WFM layer is greater than a concentration of the second metallic material in the bimetallic nitride layer.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the first WFM layer is a p-type WFM layer and the second WFM layer is an n-type WFM layer.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein a concentration profile of the first metallic material in the bimetallic nitride layer has a decreasing slope from a bottom surface to a top surface of the bimetallic nitride layer.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein a concentration of the first metallic material is greater than a concentration of the second metallic material in the bimetallic nitride layer.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein a concentration of the first metallic material in the bimetallic nitride layer ranges from about 2 atomic % to about 10 atomic %.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein a concentration ratio of the first metallic material in the metal doped region to a metal in an undoped region of the HK gate dielectric layer ranges from about 0.05 to about 0.5.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein a thickness of the metal doped region is greater than a thickness of the bimetallic nitride layer.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the first metallic material comprises aluminum and the second metallic material comprises titanium.

### Claim 11

A semiconductor device, comprising:
a substrate;
a p-type FET with a first gate structure disposed on the substrate; and
an n-type FET with a second gate structure disposed on the substrate,
wherein the first and second gate structures comprise:
high-K (HK) gate dielectric layers with metal doped regions having dopants of a first metal,
n-type work function metal (nWFM) layers disposed on the HK gate dielectric layers, and
gate metal fill layers disposed on the nWFM layers, and
wherein the first gate structure comprises a p-type work function metal (pWFM) layer and a bimetallic nitride layer interposed between the HK gate dielectric layer and the nWFM layer, the pWFM layer having a second metal and the bimetallic nitride layer having the first and second metals.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the first metal comprises aluminum.

### Claim 13 (depends on 11)

The semiconductor device of claim 11, wherein a concentration of the first metal is greater than a concentration of the second metal in the bimetallic nitride layer.

### Claim 14 (depends on 11)

The semiconductor device of claim 11, wherein a concentration of the first metal in the metal doped region is greater than a concentration of the first metal in the bimetallic nitride layer.

### Claim 15

A method, comprising:
forming a nanostructured channel region on a fin structure;
forming a gate opening surrounding the nanostructured channel region;
depositing a high-K (HK) gate dielectric layer within the gate opening, wherein the HK gate dielectric layer comprises a first metal;
forming a metal doped region with dopants of a second metal within the HK gate dielectric layer, wherein the second metal is different from the first metal;
forming a bimetallic nitride layer on the HK gate dielectric layer;
depositing a p-type work function metal (pWFM) layer on the bimetallic nitride layer, wherein the pWFM layer comprises a third metal different from the first and second metals and the bimetallic nitride layer comprises the second and third metals;
depositing an n-type work function metal (nWFM) layer on the pWFM layer; and
depositing a gate metal fill layer on the nWFM layer.

### Claim 16 (depends on 15)

The method of claim 15, wherein the forming the metal doped region comprises:
performing a first soaking process with a precursor of the third metal on the HK gate dielectric layer; and
performing a second soaking process after the first soaking process with a precursor of the second metal on the HK gate dielectric layer.

### Claim 17 (depends on 15)

The method of claim 15, wherein the forming the metal doped region comprises doping a region of the HK gate dielectric layer with the second metal and wherein the metal doped region comprises a second metal-to-first metal concentration ratio of about 0.05 to about 0.5.

### Claim 18 (depends on 15)

The method of claim 15, wherein the forming the bimetallic nitride layer comprises:
depositing a first metal layer comprising the third metal on the HK gate dielectric layer;
depositing a second metal layer on the first metal layer, wherein the second metal layer comprises the second metal; and
converting the first metal layer into a third metal layer during the depositing of the second metal layer, wherein third metal layer comprises the second and third metals.

### Claim 19 (depends on 15)

The method of claim 15, wherein the forming the bimetallic nitride layer comprises forming the bimetallic nitride layer with a concentration of the second metal greater than a concentration of the third metal.

### Claim 20 (depends on 15)

The method of claim 15, wherein the forming the bimetallic nitride layer comprises forming the bimetallic nitride layer with a concentration of the second metal less than a concentration of the second metal in the metal doped region.