# US 11,444,197 B2 · Semiconductor device and method

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- Number: US 11,444,197 B2
- Document ID: US11444197B2
- Status: Granted
- Kind: B2
- Application number: 16/785,247
- Filed: 2020-02-07
- Published: 2021-08-12
- Granted: 2022-09-13
- Earliest claimed: 2020-02-07
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chih-Chuan Yang; Kuo-Hsiu Hsu; Feng-Ming Chang; Kian-Long Lim; Lien Jung Hung
- Web page: https://patentgrep.com/patent/US11444197B2

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/0191: {forming stacked channels, e.g. changing their shapes or sizes}
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/834: {comprising FinFETs}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10B 10/12: {comprising a MOSFET load element}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor device including nanosheet field-effect transistors (NSFETs) in a first region and fin field-effect transistors (FinFETs) in a second region and methods of forming the same are disclosed. In an embodiment, a device includes a first memory cell, the first memory cell including a first transistor including a first channel region, the first channel region including a first plurality of semiconductor nanostructures; and a second transistor including a second channel region, the second channel region including a semiconductor fin.

## Claims

### Claim 1

A semiconductor device comprising:
a first memory cell, the first memory cell comprising:
a first transistor comprising a first channel region, the first channel region comprising a first plurality of semiconductor nanostructures; and
a second transistor comprising:
a second channel region, the second channel region comprising a semiconductor fin, wherein a top surface of the semiconductor fin is level with a top surface of a topmost semiconductor nanostructure of the first plurality of semiconductor nanostructures, wherein a bottom surface of the semiconductor fin is level with a bottom surface of a bottommost semiconductor nanostructure of the first plurality of semiconductor nanostructures; and
a source/drain region adjacent the semiconductor fin, wherein a top surface of the source/drain region is above the top surface of the semiconductor fin, and wherein a bottom surface of the source/drain region is below the bottom surface of the semiconductor fin; and
a substrate, wherein the first transistor and the second transistor are formed over the substrate, wherein the substrate comprises an anti-punch-through region in a top portion of the substrate, and wherein the anti-punch-through region extends continuously below the first channel region, the second channel region, and the source/drain region.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first transistor comprises a pull-down transistor and the second transistor comprises a pull-up transistor.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the first memory cell further comprises a third transistor comprising a third channel region, the third channel region comprising a second plurality of semiconductor nanostructures, wherein the third transistor comprises a pass-gate transistor.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the first transistor and the third transistor are disposed in an NMOS region over the semiconductor substrate, and wherein the second transistor is disposed in a PMOS region over the semiconductor substrate.

### Claim 5 (depends on 3)

The semiconductor device of claim 3, wherein the first memory cell further comprises:
a fourth transistor comprising a fourth channel region, the fourth channel region comprising a third plurality of semiconductor nanostructures, wherein the fourth transistor comprises a read pull-down transistor; and
a fifth transistor comprising a fifth channel region, the fifth channel region comprising a fourth plurality of semiconductor nanostructures, wherein the fifth transistor comprises a read pass-gate transistor.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein a ratio of a width of the first channel region in a direction of a current flow across the first channel region to a width of the second channel region in a direction of a current flow across the second channel region is from 3 to 8.

### Claim 7

A method comprising:
forming a multi-layer semiconductor stack over a semiconductor substrate, the multi-layer semiconductor stack comprising alternating layers of a first semiconductor material and a second semiconductor material different from the first semiconductor material, the multi-layer semiconductor stack comprising a first etch stop layer of the first semiconductor material and a second etch stop layer of the second semiconductor material;
etching the multi-layer semiconductor stack to form a first opening exposing the semiconductor substrate;
forming a third semiconductor material filling the first opening;
removing the first etch stop layer;
etching the multi-layer semiconductor stack and the semiconductor substrate to form a first nanostructure extending from the semiconductor substrate;
etching the third semiconductor material and the semiconductor substrate to form a first fin extending from the semiconductor substrate;
removing the second etch stop layer;
forming shallow trench isolation (STI) regions adjacent the first nanostructure and the first fin;
forming a first gate stack over the first nanostructure;
forming a second gate stack over the first fin;
etching the first nanostructure to form a first recess adjacent the first gate stack, the first recess extending through the first nanostructure and into the semiconductor substrate, wherein the first recess extends below top surfaces of the STI regions; and
etching the first fin to form a second recess adjacent the second gate stack, the second recess extending through the first fin and into the semiconductor substrate, wherein the second recess extends below the top surfaces of the STI regions.

### Claim 8 (depends on 7)

The method of claim 7, further comprising forming one or more third recesses by etching the multi-layer semiconductor stack to remove the alternating layers of the multi-layer semiconductor stack comprising the second semiconductor material, wherein the first semiconductor material and the third semiconductor material comprise silicon, and wherein the second semiconductor material comprises silicon germanium.

### Claim 9 (depends on 8)

The method of claim 8, wherein the first gate stack is formed filling the third recesses and extending along top surfaces and sidewalls of the first nanostructure.

### Claim 10 (depends on 7)

The method of claim 7, further comprising planarizing the multi-layer semiconductor stack and the third semiconductor material, wherein a top surface of the first nanostructure is level with a top surface of the first fin.

### Claim 11 (depends on 7)

The method of claim 7, wherein etching the multi-layer semiconductor stack and the semiconductor substrate to form the first nanostructure and etching the third semiconductor material and the semiconductor substrate to form the first fin are performed simultaneously.

### Claim 12 (depends on 7)

The method of claim 7, further comprising:
epitaxially growing a first source/drain region in the first recess; and
epitaxially growing a second source/drain region in the second recess.

### Claim 13 (depends on 12)

The method of claim 12, wherein etching the first nanostructure and etching the first fin are performed simultaneously and epitaxially growing the first source/drain region and epitaxially growing the second source/drain region are performed simultaneously.

### Claim 14

A semiconductor device comprising:
a first nanostructure extending from a semiconductor substrate in a first region of the semiconductor substrate, the first nanostructure comprising a plurality of semiconductor layers over the semiconductor substrate;
a first fin extending from the semiconductor substrate in a second region of the semiconductor substrate, the first fin comprising a semiconductor material over the semiconductor substrate, the semiconductor material having a constant composition, a top surface of the semiconductor material being level with a top surface of a topmost semiconductor layer of the plurality of semiconductor layers, a bottom surface of the semiconductor material being level with a bottom surface of a bottommost semiconductor layer of the plurality of semiconductor layers;
a first gate stack extending over the first nanostructure, the first gate stack having a longitudinal axis extending in a first direction, wherein the first nanostructure has a first width in the first direction from 10 nm to 40 nm, and wherein the first fin has a second width in the first direction from 6 nm to 8 nm;
a second gate stack extending over the first fin, the second gate stack having a longitudinal axis extending in the first direction, the second gate stack being separated from the first gate stack by a gap in the first direction; and
a first epitaxial source/drain region adjacent the first gate stack, wherein the semiconductor substrate comprises an anti-punch through region in an upper region of the semiconductor substrate, wherein the anti-punch-through region extends continuously below the first nanostructure, the first fin, and the first epitaxial source/drain region.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein first the gate stack extends along the top surface, sidewalls, and a bottom surface of the topmost semiconductor layer, the first gate stack extends along a top surface and sidewalls of the bottommost semiconductor layer, and the second gate stack extends along the top surface and sidewalls of the semiconductor material.

### Claim 16 (depends on 14)

The semiconductor device of claim 14, wherein the first region comprises an NMOS region and the second region comprises a PMOS region.

### Claim 17 (depends on 14)

The semiconductor device of claim 14, wherein a ratio of the first width of the first nanostructure to the second width of the first fin is from 3 to 8.

### Claim 18 (depends on 14)

The semiconductor device of claim 14, wherein the semiconductor material and each semiconductor layer of the plurality of semiconductor layers comprise silicon.

### Claim 19 (depends on 14)

The semiconductor device of claim 14, wherein the first epitaxial source/drain region contacts the semiconductor layers of the plurality of semiconductor layers, wherein the semiconductor device further comprises:
a second epitaxial source/drain region adjacent the second gate stack, wherein the second epitaxial source/drain region contacts the semiconductor material.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, further comprising inner spacers extending between adjacent semiconductor layers of the plurality of semiconductor layers, the inner spacers separating the first epitaxial source/drain region from the first gate stack.