# US 11,444,195 B2 · Method for fabricating semiconductor device with asymmetric strained source/drain structure

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- Number: US 11,444,195 B2
- Document ID: US11444195B2
- Status: Granted
- Kind: B2
- Application number: 17/118,524
- Filed: 2020-12-10
- Published: 2021-04-01
- Granted: 2022-09-13
- Earliest claimed: 2019-01-14
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Po-Yu Yang
- Web page: https://patentgrep.com/patent/US11444195B2

## CPC

- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/608: {having non-planar bodies, e.g. having recessed gate electrodes}
- H10D 30/796: {having memorised stress for introducing strain in the channel regions, e.g. recrystallised polysilicon gates}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10P 32/1406: {by ion implantation}
- H10P 32/171: {being group IV material}
- H10P 50/00: Etching of wafers, substrates or parts of devices
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/208: {of electrically inactive species}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of forming a semiconductor structure is disclosed. First, a substrate is provided, including an upper surface. A gate structure is disposed on the upper surface. A spacer is disposed on a sidewall of the gate structure. A first region is located in the substrate. A second region is located in the substrate. The first region and the second region are dry etched to form a first trench and a second trench, respectively. The second region is masked. The first region is then wet etched through the first trench to form a widened first trench. A stress-inducing layer is then formed in the widened first trench and in the second trench.

## Claims

### Claim 1

A method for forming a semiconductor structure, comprising:
providing a substrate having an upper surface, a gate structure on the upper surface, spacers on sidewalls of the gate structure, a first region in the substrate, and a second region in the substrate, wherein the first region and the second region are disposed on opposite sides of the gate structure, and the first region and the second region are disposed right next to the gate structure;
dry etching the first region and the second region to form a first trench in the first region and a second trench in the second region, respectively;
blanket depositing a mask layer on the substrate, wherein the mask layer covers the gate structure, the spacers, and the first region, and the second region;
removing a portion of the mask layer to expose the first trench in the first region, wherein the second trench is filled with the mask layer;
wet etching the first region through the first trench to form a widened first trench;
after wet etching the first region, removing the mask layer; and
after removing the mask layer, forming a stress-inducing layer in the second trench and the widened first trench.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the widened first trench has a hexagonal cross-sectional profile.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the stress-inducing layer comprises a SiGe layer.