# US 11,444,194 B2 · LDMOS with enhanced safe operating area and method of manufacture

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- Number: US 11,444,194 B2
- Document ID: US11444194B2
- Status: Granted
- Kind: B2
- Application number: 17/177,953
- Filed: 2021-02-17
- Published: 2022-05-05
- Granted: 2022-09-13
- Earliest claimed: 2020-11-04
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.; Tsmc China Company Limited
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.; Tsmc China Company, Limited
- Inventors: Lianjie Li; Feng Han; Jian-Hua Lu; YanBin Lu; Shui Liang Chen
- Web page: https://patentgrep.com/patent/US11444194B2

## CPC

- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/0281: {of lateral DMOS [LDMOS] FETs}
- H10D 30/0285: {using formation of insulating sidewall spacers}
- H10D 62/378: {Contact regions to the substrate regions}
- H10D 64/01: Manufacture or treatment
- H10D 64/111: {Field plates}
- H10D 64/112: {comprising multiple field plate segments}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An integrated circuit comprising an n-type drift region, a gate structure directly on a first portion of the n-type drift region, a drain structure formed in a second portion of the n-type drift region, the gate structure and the drain structure being separated by a drift region length, a resist protective oxide (RPO) formed over a portion of the n-type drift region between the gate structure and the drain structure, a field plate contact providing a direct electrical connection to the resist protective oxide.

## Claims

### Claim 1

An integrated circuit comprising:
an n-type drift region;
a gate structure on a first portion of the n-type drift region;
a drain structure in a second portion of the n-type drift region, the gate structure and the drain structure being separated by a drift region length (Lds);
a resist protective oxide (RPO) over the n-type drift region and between the gate structure and the drain structure;
a field plate contact in direct electrical connection to the resist protective oxide and configured for applying a voltage to the resist protective oxide;
a drain structure contact in direct electrical connection with the drain structure, the drain structure contact and the field plate contact being separated by a dielectric region; and
a conductive pattern over the dielectric region and electrically connecting the drain structure contact and the field plate contact.

### Claim 2 (depends on 1)

The integrated circuit according to claim 1, wherein:
the voltage is a drain voltage configured to be applied to both the field plate contact and the drain structure contact.

### Claim 3 (depends on 1)

The integrated circuit according to claim 1, wherein:
the field plate contact is separated from the gate structure by a first distance (D1), with the first distance being at least 35% of the Lds.

### Claim 4 (depends on 3)

The integrated circuit according to claim 3, wherein:
the first distance is between 40% and 70% of the Lds.

### Claim 5 (depends on 1)

The integrated circuit according to claim 1, wherein:
the field plate contact has a contact width (D3), and
the contact width is between 10% and 30% of the Lds.

### Claim 6 (depends on 1)

The integrated circuit according to claim 1, wherein:
the field plate contact comprises a first field plate contact having a first contact width and a second field plate contact having a second contact width,
the first contact width is at least 10% of the Lds, and
the second contact width is at least 10% of the Lds.

### Claim 7 (depends on 1)

The integrated circuit according to claim 1, wherein:
the resist protective oxide has an RPO thickness (D2), and
the RPO thickness is at least 10% of the Lds.

### Claim 8 (depends on 1)

The integrated circuit according to claim 1, wherein:
the resist protective oxide has an RPO thickness (D2); and
wherein the RPO thickness is between 0.05 μm and 0.2 μm.

### Claim 9 (depends on 1)

The integrated circuit according to claim 1, wherein:
the Lds is at least 0.5 μm.

### Claim 10

A method of manufacturing an integrated circuit comprising:
implanting a deep P-well in a P-type substrate;
implanting an n-type drift region in the deep P-well;
depositing a gate structure on a first portion of the n-type drift region;
implanting a drain structure in a second portion of the n-type drift region, the gate structure and the drain structure being separated by a drift region length (Lds);
depositing a resist protective oxide (RPO) over a third portion of the n-type drift region between the gate structure and the drain structure;
depositing a first dielectric layer over the resist protective oxide and the drain structure;
etching a field plate contact opening in the first dielectric layer to expose a surface portion of the resist protective oxide;
etching a drain structure contact opening in the first dielectric layer to expose a surface portion of the drain structure;
depositing a field plate contact in the field plate contact opening for providing a direct electrical connection to the resist protective oxide;
depositing a drain structure contact in the drain structure contact opening in direct electrical connection with the drain structure, wherein the drain structure contact and the field plate contact are separated by a residual portion of the first dielectric layer; and
forming a conductive pattern in electrical contact with both the field plate contact and the drain structure contact.

### Claim 11 (depends on 10)

The method of manufacturing an integrated circuit according to claim 10, further comprising:
depositing a second dielectric layer over the field plate contact and the drain structure contact;
forming a jumper opening in the second dielectric layer and exposing upper surfaces of both the field plate contact and the drain structure contact; and
depositing a conductive material in the jumper opening to establish an electrical connection between the field plate contact and the drain structure contact.

### Claim 12 (depends on 10)

The method of manufacturing an integrated circuit according to claim 10, further comprising:
forming the resist protective oxide (RPO) over a portion of the gate structure.

### Claim 13 (depends on 10)

The method of manufacturing an integrated circuit according to claim 10, further comprising:
forming sidewall structures adjacent the gate structure.

### Claim 14 (depends on 10)

The method of manufacturing an integrated circuit according to claim 10, further comprising:
defining a plurality of active areas on the P-type substrate;
forming field oxide (FOX) structures between adjacent active areas; and
positioning the field plate contact closer to the drain structure than to the gate structure.

### Claim 15 (depends on 10)

The method of manufacturing an integrated circuit according to claim 10, further comprising:
positioning the field plate contact on the resist protective oxide (RPO) at an offset from the gate structure of between 40% and 70% of the Lds.

### Claim 16 (depends on 10)

The method of manufacturing an integrated circuit according to claim 10, further comprising:
positioning the field plate contact on the resist protective oxide (RPO) at a contact point that is separated from the gate structure by between 40% and 70% of the Lds.

### Claim 17 (depends on 10)

The method of manufacturing an integrated circuit according to claim 10, further comprising:
forming a plurality of field plate contacts on the resist protective oxide (RPO) with the field plate contact offset from the gate structure by at least 40% of the Lds.

### Claim 18

A method of improving high-voltage performance in a LDMOS integrated circuit comprising:
depositing an insulating field plate over a portion of an n-type drift region arranged between a gate structure and a drain structure;
forming a first direct electrical contact to the insulating field plate;
forming a second direct electrical contact to the drain structure, wherein the first direct electrical contact is separated from the second direct electrical contact by a dielectric region;
forming a conductive jumper between the first direct electrical contact and the second direct electrical contact; and
applying a field plate voltage to the insulating field plate during device operation.

### Claim 19 (depends on 18)

The method improving high-voltage performance in a LDMOS integrated circuit according to claim 18, further comprising:
depositing a dielectric layer over the first and second direct electrical contacts;
forming a jumper opening in the second dielectric layer and exposing upper surfaces of both the first and second direct electrical contacts; and
depositing a conductive material in the jumper opening to form the conductive jumper, wherein the conductive jumper establishes an electrical connection between the first direct electrical contact and the second direct electrical contact.

### Claim 20 (depends on 18)

The method of improving high-voltage performance in a LDMOS integrated circuit according to claim 18, wherein:
the field plate voltage is equal to a drain voltage (Vdd) applied to the drain structure of the LDMOS integrated circuit.