# US 11,444,191 B2 · Integrated channel diode

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- Number: US 11,444,191 B2
- Document ID: US11444191B2
- Status: Granted
- Kind: B2
- Application number: 16/990,284
- Filed: 2020-08-11
- Published: 2020-11-26
- Granted: 2022-09-13
- Earliest claimed: 2014-06-09
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Christopher Boguslaw Kocon; Simon John Molloy; John Manning Savidge Neilson; Hideaki Kawahara
- Web page: https://patentgrep.com/patent/US11444191B2

## CPC

- H10D 84/143: {the built-in components being PN junction diodes}
- H10D 30/0295: {using recessing of the source electrodes}
- H10D 30/665: {having edge termination structures}
- H10D 62/109: {Reduced surface field [RESURF] PN junction structures}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/154: {Dispositions}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/112: {comprising multiple field plate segments}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10D 64/2527: {for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a vertical drift region over a drain contact region, abutted on opposite sides by RESURF trenches. A split gate is disposed over the vertical drift region. A first portion of the split gate is a gate of an MOS transistor and is located over a body of the MOS transistor over a first side of the vertical drift region. A second portion of the split gate is a gate of a channel diode and is located over a body of the channel diode over a second, opposite, side of the vertical drift region. A source electrode is electrically coupled to a source region of the channel diode and a source region of the MOS transistor.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, comprising:
forming a drain contact region adjacent a first surface of a semiconductor substrate;
forming a trench structure extending from a second opposite surface of the semiconductor substrate toward the drain contact region, the trench structure including a conductive plate and the trench structure having a first side and a second side opposite the first side;
forming a diode structure abutting the first side of the trench structure, the diode structure having a diode gate electrically coupled to the conductive plate and located directly on a gate dielectric; and
forming a transistor structure abutting the second side of the trench structure, the transistor structure having a transistor gate insulated from the conductive plate.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming an electrode layer above the first surface, the electrode layer electrically connecting the diode gate and the conductive plate.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
forming a first insulation cap that insulates the transistor gate from the electrode layer; and
forming a second insulation cap that exposes the diode gate to the electrode layer.

### Claim 4 (depends on 3)

The method of claim 3, wherein:
the diode gate has a first top surface and a second top surface farther away from the trench structure than the first top surface; and
the second insulation cap exposes the first top surface to the electrode layer and lies between the second top surface and the electrode layer.

### Claim 5 (depends on 1)

The method of claim 1, wherein the diode structure includes:
a body region abutting the first side of the trench structure; and
a source region within the body region and under the diode gate, the source region capacitively coupled to the diode gate and conductively connected to the conductive plate.

### Claim 6 (depends on 1)

The method of claim 1, wherein the transistor structure includes:
a body region abutting the second side of the trench structure; and
a source region within the body region and under the transistor gate, the source region conductively connected to the conductive plate and insulated from the transistor gate.

### Claim 7 (depends on 1)

The method of claim 1, further comprising forming a dielectric liner in the trench that insulates the conductive plate from the substrate.

### Claim 8 (depends on 2)

The method of claim 2, wherein the electrode layer is located between the diode gate and the transistor gate.

### Claim 9

A method of forming an integrated circuit, comprising:
forming a trench structure extending from a top surface of a semiconductor substrate into the substrate, the trench structure having a conductive plate and a dielectric liner between the semiconductor substrate and the conductive plate;
forming a diode having a diode gate and a first p-type region abutting a first side of the dielectric liner, the diode gate located directly on a gate dielectric;
forming a transistor having a transistor gate and a second p-type region abutting a second side of the dielectric liner; and
forming an electrode layer overlying the diode gate, the transistor gate and the conductive plate, the diode gate electrically conductively coupled to the conductive plate by the metal layer, and the transistor gate of being insulated from the electrode layer.

### Claim 10 (depends on 9)

The method of claim 9, further comprising:
forming a first insulation cap that insulates the transistor gate from the electrode layer; and
forming a second insulation cap that partially exposes the diode gate to the electrode layer.

### Claim 11 (depends on 10)

The method of claim 10, wherein the electrode layer is connected to a portion of the diode gate located between the second insulation cap and the trench structure.

### Claim 12 (depends on 9)

The method of claim 9, further comprising forming a first n-type region located between the conductive plate and the first p-type region.

### Claim 13 (depends on 9)

The method of claim 9, further comprising forming a second n-type region located between the conductive plate and the second p-type region.

### Claim 14 (depends on 9)

The method of claim 9, wherein the electrode layer is located between the diode gate and the transistor gate.

### Claim 15 (depends on 9)

The method of claim 9, further comprising forming a heavily doped layer within the semiconductor substrate, wherein a portion of the substrate having a dopant concentration less than the heavily doped layer is located between the heavily doped layer and the trench structure.

### Claim 16

A method of manufacturing a semiconductor device, comprising:
forming first and second trench structures extending from a top surface of a semiconductor substrate into the semiconductor substrate, the first and second trench structures including respective first and second conductive plates;
forming a split gate between the first and second trench structures over a gate dielectric layer, the split gate including a transistor gate and a diode gate;
forming a first body region having a first conductivity type in the semiconductor substrate abutting the first trench structure between the first trench structure and the transistor gate, and a first source region having an opposite second conductivity type within the first body region;
forming a second body region having the first conductivity type in the semiconductor substrate abutting the second trench structure between the second trench structure and the diode gate, and a second source region having the second conductivity type within the second body region;
insulating the transistor gate from the first and second conductive plates; and
forming a conductive connection between the diode gate and the first and second conductive plates.

### Claim 17 (depends on 16)

The method of claim 16, wherein the semiconductor substrate between the first and second trench structures provides a drift region having the second conductivity type between the first source region and a drain contact region at a bottom surface of the semiconductor substrate.

### Claim 18 (depends on 16)

The method of claim 16, wherein the conductive connection is provided by a source electrode that conductively connects to the first and second conductive plates and to the diode gate.

### Claim 19 (depends on 16)

The method of claim 16, wherein the transistor gate is insulated from the first and second conductive plates by a dielectric cap layer located over the transistor gate.

### Claim 20 (depends on 16)

The method of claim 16, wherein the first conductivity type is p-type and the second conductivity type is n-type.