# US 11,444,188 B2 · Quantum dot devices

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- Number: US 11,444,188 B2
- Document ID: US11444188B2
- Status: Granted
- Kind: B2
- Application number: 16/648,402
- Filed: 2017-12-21
- Published: 2020-07-02
- Granted: 2022-09-13
- Earliest claimed: 2017-12-21
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Ravi Pillarisetty; Nicole K. Thomas; Hubert C. George; Jeanette M. Roberts; Payam Amin; Zachary R. Yoscovits; Roman Caudillo; James S. Clarke
- Web page: https://patentgrep.com/patent/US11444188B2

## CPC

- H10D 30/473: {having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT}
- H10D 62/121: {oriented parallel to substrates}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/402: {Single electron transistors; Coulomb blockade transistors}
- H10D 48/3835: {Semiconductor qubit devices comprising a plurality of quantum mechanically interacting semiconductor quantum dots, e.g. Loss-DiVincenzo spin qubits}
- H10D 48/40: Devices controlled by magnetic fields
- H10D 62/812: {Single quantum well structures}
- H10D 62/814: {Quantum box structures}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/01: Manufacture or treatment
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/27: Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 52/403: {of conductive or resistive materials}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- B82Y 40/00: Manufacture or treatment of nanostructures
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; an insulating material at least partially above the fin, wherein the insulating material includes a trench above the fin; and a gate metal on the insulating material and extending into the trench.

## Claims

### Claim 1

A quantum dot device, comprising:
a base;
a fin extending away from the base, wherein the fin includes a quantum well layer;
an insulating material at least partially above the fin, wherein the insulating material includes a trench above the fin, wherein the insulating material extends down sides of the fin; and
a gate metal on the insulating material and extending into the trench,
wherein, in a direction perpendicular to a longitudinal axis of the fin and parallel to the base, a dimension of the fin is greater than a dimension of the trench.

### Claim 2 (depends on 1)

The quantum dot device of claim 1, wherein the trench has a width between 5 nanometers and 50 nanometers.

### Claim 3 (depends on 1)

The quantum dot device of claim 1, wherein the fin has a width between 50 nanometers and 150 nanometers.

### Claim 4 (depends on 1)

The quantum dot device of claim 1, wherein the fin is a first fin, the trench is a first trench, the gate metal is a first gate metal, and the quantum dot device further includes:
a second fin extending away from the base, wherein the second fin includes a quantum well layer;
the insulating material at least partially above the second fin, wherein the insulating material includes a second trench above the second fin; and
a second gate metal on the insulating material and extending into the second trench.

### Claim 5 (depends on 1)

The quantum dot device of claim 1, wherein the fin has a tapered shape that is widest proximate to the base.

### Claim 6 (depends on 1)

The quantum dot device of claim 1, wherein the base includes a semiconductor substrate, and the semiconductor substrate extends into the fin.

### Claim 7 (depends on 1)

The quantum dot device of claim 1, wherein the quantum well layer is included in a silicon/silicon germanium material stack.

### Claim 8 (depends on 1)

The quantum dot device of claim 1, wherein the gate metal has a length, along the fin, between 20 nanometers and 40 nanometers.

### Claim 9 (depends on 1)

The quantum dot device of claim 1, wherein the gate metal is a first gate metal, and the quantum dot device further comprises:
a second gate metal extending into the trench, wherein a spacer material is between the first gate metal and the second gate metal.

### Claim 10 (depends on 1)

The quantum dot device of claim 1, wherein the fin has a height between 250 nanometers and 350 nanometers.

### Claim 11 (depends on 1)

The quantum dot device of claim 1, wherein the trench has a tapered profile that is narrowest proximate to the fin.

### Claim 12 (depends on 1)

The quantum dot device of claim 1, further comprising:
a gate dielectric at a bottom of the trench.

### Claim 13 (depends on 1)

The quantum dot device of claim 1, wherein the trench has a depth between 100 nanometers and 300 nanometers.

### Claim 14 (depends on 1)

The quantum dot device of claim 1, wherein the fin is at a bottom of the trench.

### Claim 15 (depends on 1)

The quantum dot device of claim 1, wherein the gate metal does not extend along sidewalls of the fin.

### Claim 16 (depends on 1)

The quantum dot device of claim 1, wherein:
the quantum well layer extends, in a direction parallel to the base, between a first sidewall of the fin and an opposing second sidewall of the fin, and
the quantum well layer is below a top surface of the fin.

### Claim 17 (depends on 1)

The quantum dot device of claim 1, wherein the quantum well layer does not wrap around sidewalls and a top surface of the fin.

### Claim 18

A quantum computing device, comprising:
a quantum processing device, comprising:
a base,
a fin extending away from the base, wherein the fin includes a quantum well layer,
an insulating material at least partially above the fin, wherein the insulating material includes a trench above the fin, wherein the insulating material extends down sides of the fin, and
a gate, comprising a gate metal on the insulating material, the gate metal extending into the trench,
wherein, in a direction perpendicular to a longitudinal axis of the fin and parallel to the base, a dimension of the fin is greater than a dimension of the trench; and
a non-quantum processing device, coupled to the quantum processing device, to control voltages applied to the gate.

### Claim 19 (depends on 18)

The quantum computing device of claim 18, further comprising:
a memory device to store data generated by quantum dots formed in the quantum well stack during operation of the quantum processing device.

### Claim 20 (depends on 19)

The quantum computing device of claim 19, wherein the memory device is to store instructions for a quantum computing algorithm to be executed by the quantum processing device.

### Claim 21 (depends on 18)

The quantum computing device of claim 18, further comprising:
a cooling apparatus to maintain a temperature of the quantum processing device below 5 Kelvin.

### Claim 22

A method of manufacturing a quantum dot device, the method comprising:
providing a fin extending away from a base, wherein the fin includes a quantum well layer;
providing an insulating material at least partially above the tin, wherein the insulating material includes a trench above the fin, wherein insulating material extends down sides of the fin; and
providing a gate metal on the insulating material and extending into the trench, wherein, in a direction perpendicular to a longitudinal axis of the fin and parallel to the base, a dimension of the fin is greater than a dimension of the trench.

### Claim 23 (depends on 22)

The method of claim 22, wherein:
the quantum well layer extends, in a direction parallel to the base, between a first sidewall of the fin and an opposing second sidewall of the fin, and
the quantum well layer is below a top surface of the fin.

### Claim 24 (depends on 22)

The method of claim 22, wherein the fin is at a bottom of the trench.